Processor SIMD units supported by the math.vectors.simd vocabulary represent boolean values as bitmasks, where a true result's binary representation is all ones and a false representation is all zeroes. This is the format in which results from comparison words such as v= return their results and in which logic and test words such as vand and vall? take their inputs when working with SIMD types. For a float vector, false will manifest itself as 0.0 and true as a NAN: literal with a string of on bits in its payload:

For an integer vector, false will manifest as 0 and true as -1 (for signed vectors) or the largest representable value of the element type (for unsigned vectors):

This differs from Factor's native representation of boolean values, where f is false and every other value (including 0 and 0.0 ) is true. To make it easy to construct literal SIMD masks, t and f are accepted inside SIMD literal syntax and expand to the proper true or false representation for the underlying type:

However, extracting an element from a boolean SIMD vector with nth will not yield a valid Factor boolean. This is not generally a problem, since the results of vector comparisons are meant to be consumed by subsequent vector logical and test operations, which will accept SIMD values in the native boolean format.

Providing a SIMD boolean vector with element values other than the proper true and false representations as an input to the vector logical or test operations is undefined. Do not count on operations such as vall? or v? using bitwise operations to construct their results.

This applies to the output of the following element comparison words:

This likewise applies to the mask argument of v? and to the inputs and outputs of the following element logic words:

Finally, this applies to the inputs of these vector test words:

USING: math.vectors math.vectors.simd prettyprint ;
float-4{ 1.0 2.0 3.0 0/0. } float-4{ 1.0 -2.0 3.0 0/0. } v= .

float-4{ NAN: -20000000 0.0 NAN: -20000000 0.0 }

float-4{ NAN: -20000000 0.0 NAN: -20000000 0.0 }

For an integer vector, false will manifest as 0 and true as -1 (for signed vectors) or the largest representable value of the element type (for unsigned vectors):

USING: math.vectors math.vectors.simd prettyprint alien.c-types ;
int-4{ 1 2 3 0 } int-4{ 1 -2 3 4 } v=
uchar-16{ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 }
uchar-16{ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 } v<
[ . ] bi@

int-4{ -1 0 -1 0 } uchar-16{ 255 255 255 255 255 255 255 255 0 0 0 0 0 0 0 0 }

int-4{ -1 0 -1 0 } uchar-16{ 255 255 255 255 255 255 255 255 0 0 0 0 0 0 0 0 }

This differs from Factor's native representation of boolean values, where f is false and every other value (including 0 and 0.0 ) is true. To make it easy to construct literal SIMD masks, t and f are accepted inside SIMD literal syntax and expand to the proper true or false representation for the underlying type:

USING: math.vectors math.vectors.simd prettyprint alien.c-types ;
int-4{ f f t f } .

int-4{ 0 0 -1 0 }

int-4{ 0 0 -1 0 }

However, extracting an element from a boolean SIMD vector with nth will not yield a valid Factor boolean. This is not generally a problem, since the results of vector comparisons are meant to be consumed by subsequent vector logical and test operations, which will accept SIMD values in the native boolean format.

Providing a SIMD boolean vector with element values other than the proper true and false representations as an input to the vector logical or test operations is undefined. Do not count on operations such as vall? or v? using bitwise operations to construct their results.

This applies to the output of the following element comparison words:

• | v< |

• | v<= |

• | v= |

• | v>= |

• | v> |

• | vunordered? |

This likewise applies to the mask argument of v? and to the inputs and outputs of the following element logic words:

• | vand |

• | vandn |

• | vor |

• | vxor |

• | vnot |

Finally, this applies to the inputs of these vector test words:

• | vall? |

• | vany? |

• | vnone? |

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Factor 0.99 x86.64 (2203, heads/master-424edf64aa, Mar 8 2023 13:48:50)