Handbook
Glossary
Vector component- and bit-wise logic
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Vector shuffling, packing, and unpacking
Notes
See
Componentwise logic with SIMD vectors
for notes about using comparison and logical operations with SIMD vector types.
Element comparisons:
v<
( u v -- w )
v<=
( u v -- w )
v=
( u v -- w )
v>=
( u v -- w )
v>
( u v -- w )
vunordered?
( u v -- w )
vmax
( u v -- w )
vmin
( u v -- w )
vclamp
( v min max -- w )
vmaximum
( seq -- vmax )
vminimum
( seq -- vmin )
Bitwise operations:
vbitand
( u v -- w )
vbitandn
( u v -- w )
vbitor
( u v -- w )
vbitxor
( u v -- w )
vbitnot
( v -- w )
vlshift
( v n -- w )
vrshift
( v n -- w )
Element logical operations:
vand
( u v -- w )
vandn
( u v -- w )
vor
( u v -- w )
vxor
( u v -- w )
vnot
( v -- w )
v?
( mask true false -- result )
vif
( mask true-quot: ( -- vector ) false-quot: ( -- vector ) -- result )
Entire vector tests:
vall?
( v -- ? )
vany?
( v -- ? )
vnone?
( v -- ? )
Element shuffling:
vshuffle
( v perm -- w )