insn-available? ( ## -- reps )

Vocabulary

compiler.cfg.intrinsics.simd.backend

Inputs

##

an object

Outputs

reps

an object

Definition

IN: compiler.cfg.intrinsics.simd.backend

GENERIC: insn-available? ( ## -- reps )

Methods

USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##abs-vector insn-available? rep>> %abs-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##add-sub-vector insn-available?
    rep>> %add-sub-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##add-vector insn-available? rep>> %add-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##and-vector insn-available? rep>> %and-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##andn-vector insn-available?
    rep>> %andn-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##avg-vector insn-available? rep>> %avg-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture kernel
sequences ;

M: ##compare-vector insn-available?
    [ rep>> ] [ cc>> ] bi %compare-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##div-vector insn-available? rep>> %div-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##dot-vector insn-available? rep>> %dot-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##fill-vector insn-available?
    rep>> %fill-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##float-pack-vector insn-available?
    rep>> %float-pack-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##float>integer-vector insn-available?
    rep>> %float>integer-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##gather-int-vector-2 insn-available?
    rep>> %gather-int-vector-2-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##gather-int-vector-4 insn-available?
    rep>> %gather-int-vector-4-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##gather-vector-2 insn-available?
    rep>> %gather-vector-2-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##gather-vector-4 insn-available?
    rep>> %gather-vector-4-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##horizontal-add-vector insn-available?
    rep>> %horizontal-add-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##horizontal-shl-vector-imm insn-available?
    rep>> %horizontal-shl-vector-imm-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##horizontal-shr-vector-imm insn-available?
    rep>> %horizontal-shr-vector-imm-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##horizontal-sub-vector insn-available?
    rep>> %horizontal-sub-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##integer>float-vector insn-available?
    rep>> %integer>float-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##max-vector insn-available? rep>> %max-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##merge-vector-head insn-available?
    rep>> %merge-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##merge-vector-tail insn-available?
    rep>> %merge-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##min-vector insn-available? rep>> %min-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##move-vector-mask insn-available?
    rep>> %move-vector-mask-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##mul-high-vector insn-available?
    rep>> %mul-high-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##mul-horizontal-add-vector insn-available?
    rep>> %mul-horizontal-add-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##mul-vector insn-available? rep>> %mul-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##not-vector insn-available? rep>> %not-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##or-vector insn-available? rep>> %or-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##sad-vector insn-available? rep>> %sad-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##saturated-add-vector insn-available?
    rep>> %saturated-add-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##saturated-mul-vector insn-available?
    rep>> %saturated-mul-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##saturated-sub-vector insn-available?
    rep>> %saturated-sub-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##select-vector insn-available?
    rep>> %select-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##shl-vector-imm insn-available?
    rep>> %shl-vector-imm-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##shl-vector insn-available? rep>> %shl-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##shr-vector-imm insn-available?
    rep>> %shr-vector-imm-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##shr-vector insn-available? rep>> %shr-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##shuffle-vector-halves-imm insn-available?
    rep>> %shuffle-vector-halves-imm-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##shuffle-vector-imm insn-available?
    rep>> %shuffle-vector-imm-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##shuffle-vector insn-available?
    rep>> %shuffle-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##signed-pack-vector insn-available?
    rep>> %signed-pack-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##sqrt-vector insn-available?
    rep>> %sqrt-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##store-memory-imm insn-available?
    rep>> %alien-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##sub-vector insn-available? rep>> %sub-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##tail>head-vector insn-available?
    rep>> %unpack-vector-head-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##test-vector insn-available?
    rep>> %test-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##unpack-vector-head insn-available?
    rep>> %unpack-vector-head-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##unpack-vector-tail insn-available?
    rep>> %unpack-vector-tail-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##unsigned-pack-vector insn-available?
    rep>> %unsigned-pack-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##xor-vector insn-available? rep>> %xor-vector-reps member? ;


USING: accessors compiler.cfg.instructions
compiler.cfg.intrinsics.simd.backend cpu.architecture sequences
;

M: ##zero-vector insn-available?
    rep>> %zero-vector-reps member? ;


USING: compiler.cfg.intrinsics.simd.backend kernel ;

M: object insn-available? drop t ;