arm.64

Vocabulary

system

Definition

IN: system

SINGLETON: arm.64

Methods

USING: cpu.architecture kernel system ;

M: arm.64 %abs-vector 3drop ;


USING: cpu.architecture system ;

M: arm.64 %abs-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %add rot ADDr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %add-float rot D FADDs ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %add-imm spin ADDi ;


USING: cpu.architecture kernel system ;

M: arm.64 %add-sub-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %add-sub-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %add-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %add-vector-reps f ;


USING: cpu.architecture generalizations system ;

M: arm.64 %alien-assembly 8 ndrop ;


USING: cpu.architecture kernel system ;

M: arm.64 %alien-global 3drop ;


USING: cpu.architecture generalizations system ;

M: arm.64 %alien-indirect 9 ndrop ;


USING: cpu.architecture generalizations system ;

M: arm.64 %alien-invoke 10 ndrop ;


USING: cpu.architecture system ;

M: arm.64 %alien-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %allot 4drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %and rot ANDr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %and-imm spin ANDi ;


USING: cpu.architecture kernel system ;

M: arm.64 %and-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %and-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %andn-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %andn-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %avg-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %avg-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %bit-count
    D0 XD FMOVgen D0 D0 8B CNT D0 D0 8B ADDV D0 swap DX FMOVgen
    ;


USING: cpu.architecture cpu.arm.64.assembler kernel math system
;

M: arm.64 %bit-test [ 2^ swap TSTi ] dip swap dup EQ CSEL ;


USING: cpu.architecture kernel system ;

M: arm.64 %box 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %box-alien 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %box-displaced-alien 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %box-long-long 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %c-invoke 3drop ;


USING: compiler.codegen.relocation compiler.constants
cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %call
    -16 stack-reg stack-reg STRpre 0 BL
    rc-relative-arm64-branch rel-word-pic
    16 stack-reg stack-reg LDRpost ;


USING: cpu.architecture kernel system ;

M: arm.64 %call-gc drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %callback-inputs 2drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %callback-outputs drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %check-nursery-branch 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %clear drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-branch 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-float-ordered 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-float-ordered-branch 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-float-unordered 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-float-unordered-branch 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-imm 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-imm-branch 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-integer-imm 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-integer-imm-branch 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-vector 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-vector-ccs nip f ;


USING: cpu.architecture kernel system ;

M: arm.64 %compare-vector-reps drop f ;


USING: cpu.architecture kernel system ;

M: arm.64 %convert-integer 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %copy 2over eq? [ 3drop ] [ 3drop ] if ;


USING: cpu.architecture kernel system ;

M: arm.64 %dispatch 2drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %div-float spin D FDIVs ;


USING: cpu.architecture kernel system ;

M: arm.64 %div-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %div-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %dot-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %dot-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %double>single-float swap D S FCVT ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler layouts
math system ;

M: arm.64 %epilogue
    cell + 16 align [ stack-reg stack-reg ADDr ] unless-zero ;


USING: cpu.architecture kernel system ;

M: arm.64 %fill-vector 2drop ;


USING: cpu.architecture system ;

M: arm.64 %fill-vector-reps f ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %fixnum-add [ rot ADDr ] fixnum-overflow ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %fixnum-mul [ rot MUL ] fixnum-overflow ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %fixnum-sub [ spin SUBr ] fixnum-overflow ;


USING: cpu.architecture kernel system ;

M: arm.64 %float-pack-vector 3drop ;


USING: cpu.architecture system ;

M: arm.64 %float-pack-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %float>integer swap D FCVTZSsi ;


USING: cpu.architecture kernel system ;

M: arm.64 %float>integer-vector 3drop ;


USING: cpu.architecture system ;

M: arm.64 %float>integer-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %gather-int-vector-2 4drop ;


USING: cpu.architecture system ;

M: arm.64 %gather-int-vector-2-reps f ;


USING: cpu.architecture generalizations system ;

M: arm.64 %gather-int-vector-4 6 ndrop ;


USING: cpu.architecture system ;

M: arm.64 %gather-int-vector-4-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %gather-vector-2 4drop ;


USING: cpu.architecture system ;

M: arm.64 %gather-vector-2-reps f ;


USING: cpu.architecture generalizations system ;

M: arm.64 %gather-vector-4 6 ndrop ;


USING: cpu.architecture system ;

M: arm.64 %gather-vector-4-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %horizontal-add-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %horizontal-add-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %horizontal-shl-vector-imm 4drop ;


USING: cpu.architecture system ;

M: arm.64 %horizontal-shl-vector-imm-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %horizontal-shr-vector-imm 4drop ;


USING: cpu.architecture system ;

M: arm.64 %horizontal-shr-vector-imm-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %horizontal-sub-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %horizontal-sub-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %inc drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %integer>float swap D SCVTFsi ;


USING: cpu.architecture kernel system ;

M: arm.64 %integer>float-vector 3drop ;


USING: cpu.architecture system ;

M: arm.64 %integer>float-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %integer>scalar 3drop ;


USING: compiler.codegen.relocation compiler.constants
cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %jump
    4 pic-tail-reg ADR 0 Br
    rc-relative-arm64-branch rel-word-pic-tail ;


USING: compiler.codegen.labels compiler.constants
cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %jump-label
    0 Br rc-relative-arm64-branch label-fixup ;


USING: cpu.architecture kernel system ;

M: arm.64 %load-double 2drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %load-float 2drop ;


USING: assocs cpu.architecture cpu.arm.64.assembler kernel math
sequences system ;

M: arm.64 %load-immediate
    [ XZR MOVr ] [
        { 0 1 2 3 } [ tuck -16 * shift 65535 bitand ] with
        map>alist [ 0 = ] reject-values
        unclip overd first2 rot MOVZ [ first2 rot MOVK ] with
        each
    ] if-zero ;


USING: cpu.architecture generalizations system ;

M: arm.64 %load-memory 7 ndrop ;


USING: cpu.architecture kernel system ;

M: arm.64 %load-memory-imm 5drop ;


USING: compiler.codegen.relocation compiler.constants
cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel layouts
system ;

M: arm.64 %load-reference
    [
        3 words rot LDRl 3 words Br
        NOP NOP rc-absolute-cell rel-literal
    ] [ \ f type-number swap MOVwi ] if* ;


USING: cpu.architecture kernel system ;

M: arm.64 %load-vector 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %local-allot 4drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %log2 over CLZ 63 over dup SUBi dup NEG ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %max 2dup CMPr rot GT CSEL ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %max-float rot D FMAXs ;


USING: cpu.architecture kernel system ;

M: arm.64 %max-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %max-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %merge-vector-head 4drop ;


USING: cpu.architecture system ;

M: arm.64 %merge-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %merge-vector-tail 4drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %min 2dup CMPr rot LT CSEL ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %min-float rot D FMINs ;


USING: cpu.architecture kernel system ;

M: arm.64 %min-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %min-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %move-vector-mask 3drop ;


USING: cpu.architecture system ;

M: arm.64 %move-vector-mask-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %mul rot MUL ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %mul-float rot D FMULs ;


USING: cpu.architecture kernel system ;

M: arm.64 %mul-high-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %mul-high-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %mul-horizontal-add-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %mul-horizontal-add-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %mul-imm XZR X9 ADDi X9 rot MUL ;


USING: cpu.architecture kernel system ;

M: arm.64 %mul-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %mul-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %neg swap NEG ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %not swap MVN ;


USING: cpu.architecture kernel system ;

M: arm.64 %not-vector 3drop ;


USING: cpu.architecture system ;

M: arm.64 %not-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %or rot ORRr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %or-imm spin ORRi ;


USING: cpu.architecture kernel system ;

M: arm.64 %or-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %or-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %peek 2drop ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler layouts
math system ;

M: arm.64 %prologue
    cell - 16 align [ stack-reg stack-reg SUBr ] unless-zero ;


USING: cpu.architecture kernel system ;

M: arm.64 %reload 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %replace 2drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %replace-imm 2drop ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %return f RET ;


USING: cpu.architecture kernel system ;

M: arm.64 %sad-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %sad-vector-reps f ;


USING: compiler.codegen.relocation compiler.constants
cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %safepoint
    3 words temp0 LDRl 0 temp0 W0 STRuoff 3 words Br
    NOP NOP rc-absolute-cell rel-safepoint ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %sar spin ASRr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %sar-imm spin ASRi ;


USING: cpu.architecture kernel system ;

M: arm.64 %saturated-add-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %saturated-add-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %saturated-mul-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %saturated-mul-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %saturated-sub-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %saturated-sub-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %save-context 2drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %scalar>integer 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %scalar>vector 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %select-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %select-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %set-slot 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %set-slot-imm 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %set-vm-field 2drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %shl spin LSLr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %shl-imm spin LSLi ;


USING: cpu.architecture kernel system ;

M: arm.64 %shl-vector 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %shl-vector-imm 4drop ;


USING: cpu.architecture system ;

M: arm.64 %shl-vector-imm-reps f ;


USING: cpu.architecture system ;

M: arm.64 %shl-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %shr spin LSRr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %shr-imm spin LSRi ;


USING: cpu.architecture kernel system ;

M: arm.64 %shr-vector 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %shr-vector-imm 4drop ;


USING: cpu.architecture system ;

M: arm.64 %shr-vector-imm-reps f ;


USING: cpu.architecture system ;

M: arm.64 %shr-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %shuffle-vector 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %shuffle-vector-halves-imm 5drop ;


USING: cpu.architecture system ;

M: arm.64 %shuffle-vector-halves-imm-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %shuffle-vector-imm 4drop ;


USING: cpu.architecture system ;

M: arm.64 %shuffle-vector-imm-reps f ;


USING: cpu.architecture system ;

M: arm.64 %shuffle-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %signed-pack-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %signed-pack-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %single>double-float swap S D FCVT ;


USING: cpu.architecture kernel system ;

M: arm.64 %slot 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %slot-imm 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %spill 3drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %sqrt swap D FSQRTs ;


USING: cpu.architecture kernel system ;

M: arm.64 %sqrt-vector 3drop ;


USING: cpu.architecture system ;

M: arm.64 %sqrt-vector-reps f ;


USING: cpu.architecture generalizations system ;

M: arm.64 %store-memory 7 ndrop ;


USING: cpu.architecture kernel system ;

M: arm.64 %store-memory-imm 5drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %sub spin SUBr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %sub-float spin D FSUBs ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %sub-imm spin SUBi ;


USING: cpu.architecture kernel system ;

M: arm.64 %sub-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %sub-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %tail>head-vector 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %test 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %test-branch 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %test-imm 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %test-imm-branch 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %test-vector 5drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %test-vector-branch 5drop ;


USING: cpu.architecture system ;

M: arm.64 %test-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %unbox 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %unbox-alien 2drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %unbox-any-c-ptr 2drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %unbox-long-long 4drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %unpack-vector-head 3drop ;


USING: cpu.architecture system ;

M: arm.64 %unpack-vector-head-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %unpack-vector-tail 3drop ;


USING: cpu.architecture system ;

M: arm.64 %unpack-vector-tail-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %unsigned-pack-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %unsigned-pack-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %vector>scalar 3drop ;


USING: cpu.architecture kernel system ;

M: arm.64 %vm-field 2drop ;


USING: cpu.architecture generalizations system ;

M: arm.64 %write-barrier 6 ndrop ;


USING: cpu.architecture kernel system ;

M: arm.64 %write-barrier-imm 5drop ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %xor rot EORr ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %xor-imm spin EORi ;


USING: cpu.architecture kernel system ;

M: arm.64 %xor-vector 4drop ;


USING: cpu.architecture system ;

M: arm.64 %xor-vector-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %zero-vector 2drop ;


USING: cpu.architecture system ;

M: arm.64 %zero-vector-reps f ;


USING: cpu.architecture system ;

M: arm.64 complex-addressing? f ;


USING: cpu.arm cpu.arm.64.assembler system ;

M: arm.64 ds-reg X27 ;


USING: cpu.architecture system ;

M: arm.64 dummy-fp-params? f ;


USING: cpu.architecture system ;

M: arm.64 dummy-int-params? f ;


USING: cpu.architecture system ;

M: arm.64 dummy-stack-params? f ;


USING: compiler.cfg.intrinsics cpu.architecture system ;

M: arm.64 enable-cpu-features
    enable-min/max enable-log2 enable-bit-test
    enable-alien-4-intrinsics enable-float-min/max
    enable-bit-count enable-float-intrinsics enable-fsqrt ;


USING: cpu.architecture system ;

M: arm.64 float-right-align-on-stack? f ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 frame-reg X29 ;


USING: cpu.architecture system ;

M: arm.64 fused-unboxing? f ;


USING: cpu.architecture system ;

M: arm.64 gc-root-offset ;


USING: cpu.architecture math.order system ;

M: arm.64 immediate-arithmetic?
    -2147483648 2147483647 between? ;


USING: continuations cpu.architecture cpu.arm.64.assembler
kernel system ;

M: arm.64 immediate-bitwise?
    [ encode-bitmask drop t ] [ 2drop f ] recover ;


USING: cpu.architecture kernel system ;

M: arm.64 immediate-comparand? drop f ;


USING: cpu.architecture kernel system ;

M: arm.64 immediate-store? drop f ;


USING: cpu.architecture system ;

M: arm.64 integer-float-needs-stack-frame? f ;


USING: cpu.architecture system ;

M: arm.64 long-long-odd-register? f ;


USING: cpu.architecture system ;

M: arm.64 long-long-on-stack? f ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 machine-registers
    {
        {
            int-regs
            {
                X0
                X1
                X2
                X3
                X4
                X5
                X6
                X7
                X8
                X9
                X10
                X11
                X12
                X13
                X14
                X15
                X19
                X20
                X21
                X22
                X23
                X24
            }
        }
        {
            float-regs
            {
                V0
                V1
                V2
                V3
                V4
                V5
                V6
                V7
                V16
                V17
                V18
                V19
                V20
                V21
                V22
                V23
                V24
                V25
                V26
                V27
                V28
                V29
                V30
                V31
            }
        }
    } ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 param-regs
    drop {
        { int-regs { X0 X1 X2 X3 X4 X5 X6 X7 X8 } }
        { float-regs { V0 V1 V2 V3 V4 V5 V6 V7 } }
    } ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 return-regs
    {
        { int-regs { X0 X1 X2 X3 X4 X5 X6 X7 X8 } }
        { float-regs { V0 V1 V2 V3 V4 V5 V6 V7 } }
    } ;


USING: cpu.architecture kernel system ;

M: arm.64 return-struct-in-registers? drop f ;


USING: cpu.arm cpu.arm.64.assembler system ;

M: arm.64 rs-reg X26 ;


USING: cpu.architecture kernel system ;

M: arm.64 stack-cleanup 2drop ;


USING: compiler.cfg.stack-frame cpu.architecture layouts math
system ;

M: arm.64 stack-frame-size (stack-frame-size) cell + 16 align ;


USING: cpu.architecture system ;

M: arm.64 struct-return-on-stack? f ;


USING: cpu.architecture system ;

M: arm.64 test-instruction? t ;


USING: cpu.architecture kernel system ;

M: arm.64 value-struct? drop f ;