arm.64

Vocabulary

system

Definition

IN: system

SINGLETON: arm.64

Methods

USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %abs-vector [ ABSv ] [ FABSv ] integer/float ;


USING: cpu.architecture system ;

M: arm.64 %abs-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %add ADDS ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %add-float FADDs ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %add-imm ADDS ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %add-vector [ ADDv ] [ FADDv ] integer/float ;


USING: cpu.architecture system ;

M: arm.64 %add-vector-reps vector-reps ;


USING: combinators cpu.architecture cpu.arm.64 kernel sequences
system ;

M:: arm.64 %alien-assembly
    ( varargs? reg-inputs stack-inputs reg-outputs dead-outputs cleanup stack-size quot -- )
    stack-inputs [ first3 %store-stack-param ] each reg-inputs
    [ first3 %store-reg-param ] each varargs?
    [ reg-inputs %prepare-var-args ] when
    quot ( -- ) call-effect reg-outputs
    [ first3 %load-reg-param ] each ;


USING: compiler.codegen.relocation compiler.constants
cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %alien-global
    [ XZR MOV ] 2dip rc-absolute-cell rel-dlsym ;


USING: compiler.codegen.gc-maps cpu.architecture cpu.arm.64
cpu.arm.64.assembler generalizations kernel system ;

M: arm.64 %alien-indirect
    8 1 nrotd [ [ ?spill-slot BLR ] curry ] dip
    [ gc-map-here ] curry compose %alien-assembly ;


USING: cpu.architecture kernel system ;

M: arm.64 %alien-invoke [ %c-invoke ] 3curry %alien-assembly ;


USING: cpu.architecture system ;

M: arm.64 %alien-vector-reps vector-reps ;


USING: classes.struct cpu.architecture cpu.arm.64.assembler
kernel layouts math namespaces system vm ;

M:: arm.64 %allot ( DST size class TEMP -- )
    VM "nursery" vm offset-of [+] :> operand DST operand LDR
    temp DST size data-alignment get align ADD temp operand STR
    temp class type-number tag-header MOV temp DST [] STR
    DST dup class type-number ADD ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %and AND ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %and-imm AND ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %and-vector drop ANDv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %and-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %andn-vector drop BICv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %andn-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %avg-vector [ SHADD ] [ UHADD ] signed/unsigned ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %avg-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M:: arm.64 %bit-count ( DST SRC -- )
    fp-temp SRC FMOV fp-temp dup CNTv fp-temp dup 0 ADDV
    DST fp-temp FMOV ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M:: arm.64 %bit-test ( DST SRC1 SRC2 TEMP -- )
    DST TEMP (%boolean) SRC1 SRC2 2 insns TBZ DST TEMP MOV ;


USING: assocs cpu.architecture cpu.arm.64 cpu.arm.64.assembler
kernel sequences system ;

M:: arm.64 %box ( DST SRC func rep gc-map -- )
    rep reg-class-of f param-regs at first SRC rep %copy
    rep int-rep? arg2 arg1 ? VM MOV func f gc-map %c-invoke
    DST int-rep %load-return ;


USING: alien compiler.codegen.labels cpu.architecture cpu.arm.64
cpu.arm.64.assembler layouts system ;

M:: arm.64 %box-alien ( DST SRC TEMP -- )
    <label> :> end DST \ f type-number MOV SRC end CBZ
    DST 5 cells alien TEMP %allot temp \ f type-number MOV
    temp DST 1 alien@ STR temp DST 2 alien@ STR SRC DST 3 alien@
    STR SRC DST 4 alien@ STR end resolve-label ;


USING: alien byte-arrays classes.algebra combinators
compiler.codegen.labels cpu.architecture cpu.arm.64
cpu.arm.64.assembler kernel layouts system ;

M:: arm.64 %box-displaced-alien
    ( DST DISP BASE TEMP base-class -- )
    <label> :> end DST BASE MOV DISP end CBZ
    DST 5 cells alien TEMP %allot temp \ f type-number MOV
    temp DST 2 alien@ STR DST DISP BASE TEMP {
        {
            [ base-class \ f class<= ]
            [ 2drop %box-displaced-alien/f ]
        }
        {
            [ base-class \ alien class<= ]
            [ %box-displaced-alien/alien ]
        }
        {
            [ base-class \ byte-array class<= ]
            [ %box-displaced-alien/byte-array ]
        }
        [ end %box-displaced-alien/dynamic ]
    } cond end resolve-label ;


USING: compiler.codegen.gc-maps compiler.codegen.relocation
cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %c-invoke [ (LDR=BLR) rel-dlsym ] dip gc-map-here ;


USING: compiler.codegen.relocation cpu.architecture
cpu.arm.64.assembler system ;

M: arm.64 %call (LDR=BLR) rel-word-pic ;


USING: compiler.codegen.gc-maps cpu.architecture memory system ;

M: arm.64 %call-gc \ minor-gc %call gc-map-here ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
sequences system ;

M: arm.64 %callback-inputs
    [ [ first3 %load-reg-param ] each ]
    [ [ first3 %load-stack-param ] each ] bi* arg1 VM MOV
    arg2 XZR MOV "begin_callback" f f %c-invoke ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler
sequences system ;

M: arm.64 %callback-outputs
    arg1 VM MOV "end_callback" f f %c-invoke
    [ first3 %store-reg-param ] each ;


USING: classes.struct combinators compiler.cfg.comparisons
cpu.architecture cpu.arm.64.assembler layouts math system vm ;

M:: arm.64 %check-nursery-branch
    ( label size cc TEMP1 TEMP2 -- )
    "nursery" vm offset-of :> offset TEMP1 VM offset [+] LDR
    TEMP1 TEMP1 size ADD TEMP2 VM offset 2 cells + [+] LDR
    TEMP1 TEMP2 CMP cc
    { { cc<= [ label BLE ] } { cc/<= [ label BGT ] } } case ;


USING: cpu.architecture kernel system ;

M: arm.64 %clear [ 297 ] dip %replace-imm ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %compare [ CMP ] [ cc>cond ] [ %boolean ] tri* ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %compare-branch [ CMP ] dip cc>cond B.cond ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %compare-float-ordered
    [ FCMPE ] 2dip (%compare-float) ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %compare-float-ordered-branch
    [ FCMPE ] dip (%compare-float-branch) ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %compare-float-unordered
    [ FCMP ] 2dip (%compare-float) ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %compare-float-unordered-branch
    [ FCMP ] dip (%compare-float-branch) ;


USING: cpu.architecture cpu.arm.64 system ;

M:: arm.64 %compare-imm ( DST SRC1 SRC2 cc TEMP -- )
    SRC1 SRC2 (%compare-imm) DST cc cc>cond TEMP %boolean ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %compare-imm-branch
    [ (%compare-imm) ] dip cc>cond B.cond ;


USING: cpu.architecture system ;

M: arm.64 %compare-integer-imm %compare ;


USING: cpu.architecture system ;

M: arm.64 %compare-integer-imm-branch %compare-branch ;


USING: combinators compiler.cfg.comparisons cpu.architecture
cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %compare-vector
    {
        { cc= [ [ CMEQ ] [ FCMEQ ] integer/float ] }
        {
            cc>
            [
                [ CMHI ] [ CMGT ] [ FCMGT ]
                signed/unsigned/float
            ]
        }
        {
            cc>=
            [
                [ CMHS ] [ CMGE ] [ FCMGE ]
                signed/unsigned/float
            ]
        }
    } case ;


USING: combinators compiler.cfg.comparisons cpu.architecture
kernel system ;

M: arm.64 %compare-vector-ccs
    nip {
        { cc< [ { { cc> t } } f ] }
        { cc<= [ { { cc>= t } } f ] }
        { cc> [ { { cc> f } } f ] }
        { cc>= [ { { cc>= f } } f ] }
        { cc= [ { { cc= f } } f ] }
        { cc<> [ { { cc= f } } t ] }
    } case ;


USING: compiler.cfg.comparisons cpu.architecture kernel
sequences system ;

M: arm.64 %compare-vector-reps
    { cc< cc<= cc> cc>= cc= cc<> } member? vector-reps and ;


USING: alien.c-types cpu.architecture cpu.arm.64.assembler
kernel math system ;

M: arm.64 %convert-integer
    [ [ 0 ] dip heap-size 1 - ] [ c-type-signed ] bi
    [ SBFM ] [ UBFM ] if ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %copy
    2over eq?
    [ 3drop ] [
        [ [ ?spill-slot ] bi@ ] dip 2over [ register? ] both?
        [ copy-register* ] [ copy-memory* ] if
    ] if ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M:: arm.64 %dispatch ( SRC TEMP -- )
    temp 3 insns ADR temp dup SRC [+] LDR temp BR ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %div-float FDIVs ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %div-vector >spec FDIVv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %div-vector-reps float-vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %dot-vector [ SDOT ] [ UDOT ] signed/unsigned ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %dot-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %double>single-float FCVT ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %epilogue ( n -- ) FP LR SP n [post] LDP ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %fill-vector drop dup dup BICv ;


USING: cpu.architecture system ;

M: arm.64 %fill-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %fixnum-add [ ADDS ] fixnum-overflow ;


USING: combinators compiler.cfg.comparisons cpu.architecture
cpu.arm.64.assembler system ;

M:: arm.64 %fixnum-mul ( label dst src1 src2 cc -- )
    temp src1 src2 SMULH dst src1 src2 MUL temp dst 63 <ASR> CMP
    label cc { { cc-o [ BNE ] } { cc/o [ BEQ ] } } case ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %fixnum-sub [ SUBS ] fixnum-overflow ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %float-pack-vector >spec FCVTN ;


USING: cpu.architecture system ;

M: arm.64 %float-pack-vector-reps { double-2-rep } ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %float>integer FCVTZSsi ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %float>integer-vector >spec* FCVTZSvi ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %float>integer-vector-reps float-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %gather-int-vector-2 ( DST SRC1 SRC2 rep -- )
    DST SRC1 0 rep INSgen DST SRC2 1 rep INSgen ;


USING: cpu.architecture system ;

M: arm.64 %gather-int-vector-2-reps
    { longlong-2-rep ulonglong-2-rep } ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %gather-int-vector-4
    ( DST SRC1 SRC2 SRC3 SRC4 rep -- )
    DST SRC1 0 rep INSgen DST SRC2 1 rep INSgen
    DST SRC3 2 rep INSgen DST SRC4 3 rep INSgen ;


USING: cpu.architecture system ;

M: arm.64 %gather-int-vector-4-reps { int-4-rep uint-4-rep } ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %gather-vector-2 ( DST SRC1 SRC2 rep -- )
    DST SRC1 0 0 rep INSelt DST SRC2 1 0 rep INSelt ;


USING: cpu.architecture system ;

M: arm.64 %gather-vector-2-reps
    { double-2-rep longlong-2-rep ulonglong-2-rep } ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %gather-vector-4
    ( DST SRC1 SRC2 SRC3 SRC4 rep -- )
    DST SRC1 0 0 rep INSelt DST SRC1 1 0 rep INSelt
    DST SRC1 2 0 rep INSelt DST SRC1 3 0 rep INSelt ;


USING: cpu.architecture system ;

M: arm.64 %gather-vector-4-reps
    { float-4-rep int-4-rep uint-4-rep } ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %horizontal-add-vector >spec ADDPv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %horizontal-add-vector-reps int-vector-reps ;


USING: accessors compiler.cfg.registers cpu.architecture
cpu.arm.64.assembler kernel layouts math system ;

M: arm.64 %inc
    [ ds-loc? DS RS ? dup ] [ n>> cells ] bi dup 0 >
    [ ADD ] [ neg SUB ] if ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %integer>float SCVTFsi ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %integer>float-vector >spec SCVTFvi ;


USING: cpu.architecture system ;

M: arm.64 %integer>float-vector-reps
    { int-4-rep longlong-2-rep } ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %integer>scalar drop FMOV ;


USING: compiler.codegen.relocation cpu.architecture
cpu.arm.64.assembler system ;

M: arm.64 %jump
    PIC-TAIL 5 insns ADR (LDR=BR) rel-word-pic-tail ;


USING: compiler.codegen.labels compiler.constants
cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %jump-label 0 B rc-relative-arm-b label-fixup ;


USING: alien.c-types alien.data cpu.architecture system ;

M: arm.64 %load-double double <ref> double-rep %load-vector ;


USING: alien.c-types alien.data cpu.architecture system ;

M: arm.64 %load-float float <ref> float-rep %load-vector ;


USING: assocs cpu.architecture cpu.arm.64.assembler kernel math
sequences system ;

M: arm.64 %load-immediate
    [ XZR MOV ] [
        4 <iota> [ [ -16 * shift 65535 bitand ] keep ] with
        map>alist [ 0 = ] reject-keys unclip overd first2 MOVZ
        [ first2 MOVK ] with each
    ] if-zero ;


USING: cpu.architecture cpu.arm.64 kernel system ;

M: arm.64 %load-memory swap or [ (%memory) ] dip copy-memory* ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %load-memory-imm swap or [ [+] ] dip copy-memory* ;


USING: compiler.codegen.relocation cpu.architecture
cpu.arm.64.assembler kernel layouts system ;

M: arm.64 %load-reference
    [ swap (LDR=) rel-literal ] [ \ f type-number MOV ] if* ;


USING: compiler.codegen.labels compiler.constants
cpu.architecture cpu.arm.64 system ;

M:: arm.64 %load-vector ( DST val rep -- )
    DST 0 rep copy-memory*
    val rc-relative-arm-b.cond/ldr rel-binary-literal ;


USING: compiler.cfg cpu.architecture cpu.arm.64
cpu.arm.64.assembler system ;

M:: arm.64 %local-allot ( DST size align offset -- )
    DST SP offset local-allot-offset special-offset ADD ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %log2 ( DST SRC -- )
    DST SRC CLZ DST DST 64 SUB DST DST MVN ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %max ( DST SRC1 SRC2 -- )
    SRC1 SRC2 CMP DST SRC1 SRC2 GE CSEL ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %max-float FMAXs ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %max-vector
    [ SMAXv ] [ UMAXv ] [ FMAXv ] signed/unsigned/float ;


USING: cpu.architecture system ;

M: arm.64 %max-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %merge-vector-head >spec TRN1 ;


USING: cpu.architecture system ;

M: arm.64 %merge-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %merge-vector-tail >spec TRN2 ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M:: arm.64 %min ( DST SRC1 SRC2 -- )
    SRC1 SRC2 CMP DST SRC1 SRC2 LE CSEL ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %min-float FMINs ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %min-vector
    [ SMINv ] [ UMINv ] [ FMINv ] signed/unsigned/float ;


USING: cpu.architecture system ;

M: arm.64 %min-vector-reps vector-reps ;


USING: cpu.architecture system ;

M: arm.64 %move-vector-mask-reps f ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %mul MUL ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %mul-float FMULs ;


USING: cpu.architecture system ;

M: arm.64 %mul-high-vector-reps f ;


USING: cpu.architecture system ;

M: arm.64 %mul-horizontal-add-vector-reps f ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M:: arm.64 %mul-imm ( DST SRC1 src2 -- )
    temp XZR MOV temp dup src2 ADD DST SRC1 temp MUL ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %mul-vector [ MULv ] [ FMULv ] integer/float ;


USING: cpu.architecture system ;

M: arm.64 %mul-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %neg NEG ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %not MVN ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %not-vector drop MVNv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %not-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %or ORR ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %or-imm ORR ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %or-vector drop ORRv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %or-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %peek loc>operand LDR ;


USING: cpu.architecture cpu.arm.64.assembler math system ;

M:: arm.64 %prologue ( n -- )
    FP LR SP n neg [pre] STP FP SP MOV ;


USING: cpu.architecture kernel system ;

M: arm.64 %reload swap %copy ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %replace loc>operand STR ;


USING: combinators compiler.codegen.relocation cpu.architecture
cpu.arm.64 cpu.arm.64.assembler kernel layouts math system ;

M:: arm.64 %replace-imm ( imm loc -- )
    imm 0 =
    [ XZR loc %replace ] [
        {
            { [ imm not ] [ temp \ f type-number MOV ] }
            { [ imm fixnum? ] [ temp imm tag-fixnum MOV ] }
            [ imm temp (LDR=) rel-literal ]
        } cond temp loc loc>operand STR
    ] if ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %return RET ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %sad-vector
    [ [ SABD ] [ UABD ] signed/unsigned ] 4keep 2nip
    dupd >spec ADDV ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %sad-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %safepoint SAFEPOINT dup [] STR ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %sar ASR ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %sar-imm ASR ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %saturated-add-vector
    [ SQADD ] [ UQADD ] signed/unsigned ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %saturated-add-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %saturated-sub-vector
    [ SQSUB ] [ UQSUB ] signed/unsigned ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %saturated-sub-vector-reps int-vector-reps ;


USING: classes.struct cpu.architecture cpu.arm.64.assembler
system vm ;

M:: arm.64 %save-context ( TEMP1 TEMP2 -- )
    TEMP1 %context TEMP2 SP MOV
    TEMP2 TEMP1 "callstack-top" context offset-of [+] STR
    DS TEMP1 "datastack" context offset-of [+] STR
    RS TEMP1 "retainstack" context offset-of [+] STR ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %scalar>integer drop FMOV ;


USING: cpu.architecture system ;

M: arm.64 %scalar>vector %copy ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %select-vector UMOV ;


USING: cpu.architecture system ;

M: arm.64 %select-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %set-slot (%slot) [+] STR ;


USING: compiler.constants cpu.architecture cpu.arm.64.assembler
system ;

M: arm.64 %set-slot-imm slot-offset [+] STR ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %set-vm-field [ VM ] dip [+] STR ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %shl LSL ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %shl-imm LSL ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %shl-vector [ SSHL ] [ USHL ] signed/unsigned ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %shl-vector-imm >spec SHL ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %shl-vector-imm-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %shl-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %shr LSR ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %shr-imm LSR ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %shr-vector
    [ 2nipd dupd >spec NEGv ] 4keep %shl-vector ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %shr-vector-imm [ SSHR ] [ USHR ] signed/unsigned ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %shr-vector-imm-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %shr-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %shuffle-vector drop TBL ;


USING: cpu.architecture kernel system ;

M: arm.64 %shuffle-vector-halves-imm 5drop ;


USING: cpu.architecture system ;

M: arm.64 %shuffle-vector-halves-imm-reps f ;


USING: cpu.architecture kernel system ;

M: arm.64 %shuffle-vector-imm 4drop ;


USING: cpu.architecture system ;

M: arm.64 %shuffle-vector-imm-reps f ;


USING: cpu.architecture system ;

M: arm.64 %shuffle-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %signed-pack-vector
    >spec [ nip SQXTN ] 4keep nipd SQXTN2 ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %signed-pack-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %single>double-float FCVT ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %slot (%slot) [+] LDR ;


USING: compiler.constants cpu.architecture cpu.arm.64.assembler
system ;

M: arm.64 %slot-imm slot-offset [+] LDR ;


USING: cpu.architecture kernel system ;

M: arm.64 %spill -rot %copy ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %sqrt FSQRTs ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %sqrt-vector >spec FSQRTv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %sqrt-vector-reps float-vector-reps ;


USING: cpu.architecture cpu.arm.64 kernel system ;

M: arm.64 %store-memory
    swap or [ (%memory) swap ] dip copy-memory* ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %store-memory-imm
    swap or [ [+] swap ] dip copy-memory* ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %sub SUBS ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %sub-float FSUBs ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %sub-imm SUBS ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M: arm.64 %sub-vector [ SUBv ] [ FSUBv ] integer/float ;


USING: cpu.architecture system ;

M: arm.64 %sub-vector-reps vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %tail>head-vector drop dupd 8 EXT ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %test [ TST ] [ cc>cond ] [ %boolean ] tri* ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %test-branch [ TST ] dip cc>cond B.cond ;


USING: cpu.architecture system ;

M: arm.64 %test-imm %test ;


USING: cpu.architecture system ;

M: arm.64 %test-imm-branch %test-branch ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M:: arm.64 %unbox ( DST SRC func rep -- )
    arg1 SRC tagged-rep %copy arg2 VM MOV func f f %c-invoke
    DST rep %load-return ;


USING: compiler.constants cpu.architecture cpu.arm.64.assembler
system ;

M: arm.64 %unbox-alien alien-offset [+] LDR ;


USING: alien compiler.codegen.labels compiler.constants
cpu.architecture cpu.arm.64.assembler layouts namespaces system
;

M:: arm.64 %unbox-any-c-ptr ( DST SRC -- )
    <label> :> end DST XZR MOV SRC \ f type-number CMP end BEQ
    DST SRC tag-mask get AND DST alien type-number CMP
    DST SRC byte-array-offset ADD end BNE
    DST SRC alien-offset [+] LDR end resolve-label ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %unpack-vector-head SXTL ;


USING: cpu.architecture system ;

M: arm.64 %unpack-vector-head-reps vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %unpack-vector-tail SHLL ;


USING: cpu.architecture system ;

M: arm.64 %unpack-vector-tail-reps vector-reps ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler kernel
system ;

M: arm.64 %unsigned-pack-vector
    >spec [ nip SQXTUN ] 4keep nipd SQXTUN2 ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %unsigned-pack-vector-reps int-vector-reps ;


USING: cpu.architecture system ;

M: arm.64 %vector>scalar %copy ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %vm-field [ VM ] dip [+] LDR ;


USING: cpu.architecture cpu.arm.64 cpu.arm.64.assembler system ;

M:: arm.64 %write-barrier
    ( SRC SLOT scale tag TEMP1 TEMP2 -- )
    TEMP1 SRC SLOT scale tag (%slot) ADD
    TEMP1 TEMP2 (%write-barrier) ;


USING: compiler.constants cpu.architecture cpu.arm.64
cpu.arm.64.assembler system ;

M:: arm.64 %write-barrier-imm
    ( SRC slot tag TEMP1 TEMP2 -- )
    TEMP1 SRC slot tag slot-offset ADD
    TEMP1 TEMP2 (%write-barrier) ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %xor EOR ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 %xor-imm EOR ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %xor-vector drop EORv ;


USING: cpu.architecture cpu.arm.64 system ;

M: arm.64 %xor-vector-reps int-vector-reps ;


USING: cpu.architecture cpu.arm.64.assembler kernel system ;

M: arm.64 %zero-vector drop dup dup EORv ;


USING: cpu.architecture system ;

M: arm.64 %zero-vector-reps vector-reps ;


USING: cpu.architecture system ;

M: arm.64 complex-addressing? t ;


USING: cpu.architecture system ;

M: arm.64 dummy-fp-params? f ;


USING: cpu.architecture system ;

M: arm.64 dummy-int-params? f ;


USING: cpu.architecture system ;

M: arm.64 dummy-stack-params? f ;


USING: compiler.cfg.intrinsics cpu.architecture system ;

M: arm.64 enable-cpu-features
    enable-min/max enable-log2 enable-bit-test
    enable-alien-4-intrinsics enable-float-min/max
    enable-bit-count enable-float-intrinsics enable-fsqrt ;


USING: cpu.architecture system ;

M: arm.64 float-right-align-on-stack? f ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 frame-reg FP ;


USING: cpu.architecture system ;

M: arm.64 fused-unboxing? t ;


USING: accessors compiler.cfg cpu.architecture cpu.arm.64
layouts math system ;

M: arm.64 gc-root-offset
    n>> spill-offset special-offset cell + cell /i ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 immediate-arithmetic? add/sub-immediate? ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 immediate-bitwise? logical-64-bit-immediate? ;


USING: cpu.architecture cpu.arm.64.assembler system ;

M: arm.64 immediate-comparand? add/sub-immediate? ;


USING: combinators cpu.architecture cpu.arm.64.assembler kernel
layouts math system ;

M: arm.64 immediate-store?
    {
        {
            [ dup fixnum? ]
            [ tag-fixnum 16 unsigned-immediate? ]
        }
        { [ dup not ] [ drop t ] }
        [ drop f ]
    } cond ;


USING: cpu.architecture system ;

M: arm.64 integer-float-needs-stack-frame? f ;


USING: cpu.architecture system ;

M: arm.64 long-long-odd-register? f ;


USING: cpu.architecture system ;

M: arm.64 long-long-on-stack? f ;


USING: cpu.architecture system ;

M: arm.64 machine-registers
    {
        {
            int-regs
            {
                X0
                X1
                X2
                X3
                X4
                X5
                X6
                X7
                X8
                X10
                X11
                X12
                X13
                X14
                X15
            }
        }
        {
            float-regs
            {
                V0
                V1
                V2
                V3
                V4
                V5
                V6
                V7
                V16
                V17
                V18
                V19
                V20
                V21
                V22
                V23
                V24
                V25
                V26
                V27
                V28
                V29
                V30
            }
        }
    } ;


USING: cpu.architecture kernel system ;

M: arm.64 param-regs
    drop {
        { int-regs { X0 X1 X2 X3 X4 X5 X6 X7 } }
        { float-regs { V0 V1 V2 V3 V4 V5 V6 V7 } }
    } ;


USING: cpu.arm.64 system ;

M: arm.64 reserved-stack-space 0 ;


USING: cpu.architecture system ;

M: arm.64 return-regs
    { { int-regs { X0 X1 } } { float-regs { V0 } } } ;


USING: alien.c-types cpu.architecture layouts math system ;

M: arm.64 return-struct-in-registers? heap-size 2 cells <= ;


USING: cpu.architecture kernel system ;

M: arm.64 stack-cleanup 3drop 0 ;


USING: compiler.cfg.stack-frame cpu.architecture layouts math
system ;

M: arm.64 stack-frame-size
    (stack-frame-size) 2 cells + 16 align ;


USING: cpu.architecture system ;

M: arm.64 struct-return-on-stack? f ;


USING: cpu.architecture system ;

M: arm.64 test-instruction? t ;


USING: cpu.architecture kernel system ;

M: arm.64 value-struct? drop t ;