Summary
cpu.arm.assembler.opcodes vocabulary
Meta-data
Words
Tuple classes
Singleton classes
Parsing words
Generic words
Symbol words
Ordinary words
Class predicate words
Files
cpu.arm.assembler.opcodes vocabulary
Meta-data
| Authors: | Doug Coleman |
Words
Tuple classes
Singleton classes
 ELR_EL1 |
| ELR_EL2 |
| ELR_EL3 |
| SPSR_EL1 |
| SPSR_EL2 |
| SPSR_EL3 |
| SP_EL0 |
| SP_EL1 |
| SP_EL2 |
| SP_EL3 |
Parsing words
| Word | Syntax |
 ARM-INSTRUCTION: | |
| FIELD: | |
| REGISTER-FIELD: | |
| REGISTERS: |
Generic words
| Word | Stack effect |
 register | ( obj -- n ) |
| value | ( obj -- n ) |
| width | ( obj -- n ) |
Symbol words
 B0 |
| B1 |
| B10 |
| B11 |
| B12 |
| B13 |
| B14 |
| B15 |
| B16 |
| B17 |
| B18 |
| B19 |
| B2 |
| B20 |
| B21 |
| B22 |
| B23 |
| B24 |
| B25 |
| B26 |
| B27 |
| B28 |
| B29 |
| B3 |
| B30 |
| B31 |
| B4 |
| B5 |
| B6 |
| B7 |
| B8 |
| B9 |
| D0 |
| D1 |
| D10 |
| D11 |
| D12 |
| D13 |
| D14 |
| D15 |
| D16 |
| D17 |
| D18 |
| D19 |
| D2 |
| D20 |
| D21 |
| D22 |
| D23 |
| D24 |
| D25 |
| D26 |
| D27 |
| D28 |
| D29 |
| D3 |
| D30 |
| D31 |
| D4 |
| D5 |
| D6 |
| D7 |
| D8 |
| D9 |
| H0 |
| H1 |
| H10 |
| H11 |
| H12 |
| H13 |
| H14 |
| H15 |
| H16 |
| H17 |
| H18 |
| H19 |
| H2 |
| H20 |
| H21 |
| H22 |
| H23 |
| H24 |
| H25 |
| H26 |
| H27 |
| H28 |
| H29 |
| H3 |
| H30 |
| H31 |
| H4 |
| H5 |
| H6 |
| H7 |
| H8 |
| H9 |
| Q0 |
| Q1 |
| Q10 |
| Q11 |
| Q12 |
| Q13 |
| Q14 |
| Q15 |
| Q16 |
| Q17 |
| Q18 |
| Q19 |
| Q2 |
| Q20 |
| Q21 |
| Q22 |
| Q23 |
| Q24 |
| Q25 |
| Q26 |
| Q27 |
| Q28 |
| Q29 |
| Q3 |
| Q30 |
| Q31 |
| Q4 |
| Q5 |
| Q6 |
| Q7 |
| Q8 |
| Q9 |
| S0 |
| S1 |
| S10 |
| S11 |
| S12 |
| S13 |
| S14 |
| S15 |
| S16 |
| S17 |
| S18 |
| S19 |
| S2 |
| S20 |
| S21 |
| S22 |
| S23 |
| S24 |
| S25 |
| S26 |
| S27 |
| S28 |
| S29 |
| S3 |
| S30 |
| S31 |
| S4 |
| S5 |
| S6 |
| S7 |
| S8 |
| S9 |
| V0 |
| V1 |
| V10 |
| V11 |
| V12 |
| V13 |
| V14 |
| V15 |
| V16 |
| V17 |
| V18 |
| V19 |
| V2 |
| V20 |
| V21 |
| V22 |
| V23 |
| V24 |
| V25 |
| V26 |
| V27 |
| V28 |
| V29 |
| V3 |
| V30 |
| V31 |
| V4 |
| V5 |
| V6 |
| V7 |
| V8 |
| V9 |
| W0 |
| W1 |
| W10 |
| W11 |
| W12 |
| W13 |
| W14 |
| W15 |
| W16 |
| W17 |
| W18 |
| W19 |
| W2 |
| W20 |
| W21 |
| W22 |
| W23 |
| W24 |
| W25 |
| W26 |
| W27 |
| W28 |
| W29 |
| W3 |
| W30 |
| W4 |
| W5 |
| W6 |
| W7 |
| W8 |
| W9 |
| X0 |
| X1 |
| X10 |
| X11 |
| X12 |
| X13 |
| X14 |
| X15 |
| X16 |
| X17 |
| X18 |
| X19 |
| X2 |
| X20 |
| X21 |
| X22 |
| X23 |
| X24 |
| X25 |
| X26 |
| X27 |
| X28 |
| X29 |
| X3 |
| X30 |
| X4 |
| X5 |
| X6 |
| X7 |
| X8 |
| X9 |
Ordinary words
| Word | Stack effect |
 <integer-literal> | ( value width -- integer-literal ) |
| >CC | ( x -- x ) |
| ?lookup-word | ( name vocab -- word ) |
| A | ( n -- n ) |
| A-range | ( value -- * ) |
| ADC32-encode | ( Rm Rn Rd -- instruction ) |
| ADC64-encode | ( Rm Rn Rd -- instruction ) |
| ADCS32-encode | ( Rm Rn Rd -- instruction ) |
| ADCS64-encode | ( Rm Rn Rd -- instruction ) |
| ADDG-encode | ( uimm6 uimm4 Xn Xd -- instruction ) |
| ADDSer32-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| ADDSer64-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| ADDSi32-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| ADDSi64-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| ADDSsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ADDSsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ADDer32-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| ADDer64-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| ADDi32-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| ADDi64-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| ADDs-encode | ( size2 Rm Rn Rd -- instruction ) |
| ADDsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ADDsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ADR-encode | ( immlo2 immhi19 Rd -- instruction ) |
| ADRP-encode | ( immlo2 immhi19 Rd -- instruction ) |
| AL | ( -- n ) |
| ANDSi32-encode | ( immrimms Rn Rd -- instruction ) |
| ANDSi64-encode | ( Nimmrimms Rn Rd -- instruction ) |
| ANDSsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ANDSsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ANDi32-encode | ( immrimms Rn Rd -- instruction ) |
| ANDi64-encode | ( Nimmrimms Rn Rd -- instruction ) |
| ANDsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ANDsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ASRV32-encode | ( Rm Rn Rd -- instruction ) |
| ASRV64-encode | ( Rm Rn Rd -- instruction ) |
| ASRi32-encode | ( immr Rn Rd -- instruction ) |
| ASRi64-encode | ( immr Rn Rd -- instruction ) |
| ASRr32-encode | ( Rm Rn Rd -- instruction ) |
| ASRr64-encode | ( Rm Rn Rd -- instruction ) |
| AT-encode | ( op3 op3 Rt -- instruction ) |
| AUTDA-encode | ( Rn Rd -- instruction ) |
| AUTDB-encode | ( Rn Rd -- instruction ) |
| AUTDZA-encode | ( Rd -- instruction ) |
| AUTDZB-encode | ( Rd -- instruction ) |
| AUTIA-encode | ( Rn Rd -- instruction ) |
| AUTIA1716-encode | ( -- instruction ) |
| AUTIAAZ-encode | ( -- instruction ) |
| AUTIASP-encode | ( -- instruction ) |
| AUTIB-encode | ( Rn Rd -- instruction ) |
| AUTIB1716-encode | ( -- instruction ) |
| AUTIBSP-encode | ( -- instruction ) |
| AUTIBZ-encode | ( -- instruction ) |
| AUTIZA-encode | ( Rd -- instruction ) |
| AUTIZB-encode | ( Rd -- instruction ) |
| AXFlag-encode | ( -- instruction ) |
| B-encode | ( imm26 -- instruction ) |
| B.cond | ( imm19 cond4 -- instruction ) |
| BFC32-encode | ( immrimms Rd -- instruction ) |
| BFC64-encode | ( Nimmrimms Rd -- instruction ) |
| BFI32-encode | ( immrimms Rn Rd -- instruction ) |
| BFI64-encode | ( Nimmrimms Rn Rd -- instruction ) |
| BFM32-encode | ( immrimms Rn Rd -- instruction ) |
| BFM64-encode | ( Nimmrimms Rn Rd -- instruction ) |
| BFXIL32-encode | ( immrimms Rn Rd -- instruction ) |
| BFXIL64-encode | ( Nimmrimms Rn Rd -- instruction ) |
| BIC-encode | ( Q a1 b1 c1 cmode4 d1 e1 f1 g1 h1 Rd -- instruction ) |
| BICSsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| BICSsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| BICsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| BICsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| BL-encode | ( imm26 -- instruction ) |
| BLR-encode | ( Rn -- instruction ) |
| BLRAA-encode | ( Rn Rm -- instruction ) |
| BLRAAZ-encode | ( Rn -- instruction ) |
| BLRAB-encode | ( Rn Rm -- instruction ) |
| BLRABZ-encode | ( Rn -- instruction ) |
| BR-encode | ( Rn -- instruction ) |
| BRAA-encode | ( Rn -- instruction ) |
| BRAAZ-encode | ( Rn Rm -- instruction ) |
| BRAB-encode | ( Rn -- instruction ) |
| BRABZ-encode | ( Rn Rm -- instruction ) |
| BRK-encode | ( imm16 -- instruction ) |
| BTI-encode | ( -- instruction ) |
| CAS32-encode | ( Rs Rn Rt -- instruction ) |
| CAS64-encode | ( Rs Rn Rt -- instruction ) |
| CASA32-encode | ( Rs Rn Rt -- instruction ) |
| CASA64-encode | ( Rs Rn Rt -- instruction ) |
| CASAB-encode | ( Rs Rn Rt -- instruction ) |
| CASAH-encode | ( Rs Rn Rt -- instruction ) |
| CASAL32-encode | ( Rs Rn Rt -- instruction ) |
| CASAL64-encode | ( Rs Rn Rt -- instruction ) |
| CASALB-encode | ( Rs Rn Rt -- instruction ) |
| CASALH-encode | ( Rs Rn Rt -- instruction ) |
| CASB-encode | ( Rs Rn Rt -- instruction ) |
| CASH-encode | ( Rs Rn Rt -- instruction ) |
| CASL32-encode | ( Rs Rn Rt -- instruction ) |
| CASL64-encode | ( Rs Rn Rt -- instruction ) |
| CASLB-encode | ( Rs Rn Rt -- instruction ) |
| CASLH-encode | ( Rs Rn Rt -- instruction ) |
| CASP32-encode | ( Rs Rn Rt -- instruction ) |
| CASP64-encode | ( Rs Rn Rt -- instruction ) |
| CASPA32-encode | ( Rs Rn Rt -- instruction ) |
| CASPA64-encode | ( Rs Rn Rt -- instruction ) |
| CASPAL32-encode | ( Rs Rn Rt -- instruction ) |
| CASPAL64-encode | ( Rs Rn Rt -- instruction ) |
| CASPL32-encode | ( Rs Rn Rt -- instruction ) |
| CASPL64-encode | ( Rs Rn Rt -- instruction ) |
| CBNZ32-encode | ( imm19 Rt -- instruction ) |
| CBNZ64-encode | ( imm19 Rt -- instruction ) |
| CBZ32-encode | ( imm19 Rt -- instruction ) |
| CBZ64-encode | ( imm19 Rt -- instruction ) |
| CC | ( -- n ) |
| CCMNi32-encode | ( imm5 cond4 Rn nzcv4 -- instruction ) |
| CCMNi64-encode | ( imm5 cond4 Rn nzcv4 -- instruction ) |
| CCMNr32-encode | ( Rm cond4 Rn nzcv4 -- instruction ) |
| CCMNr64-encode | ( Rm cond4 Rn nzcv4 -- instruction ) |
| CCMPi32-encode | ( imm5 cond4 Rn nzcv4 -- instruction ) |
| CCMPi64-encode | ( imm5 cond4 Rn nzcv4 -- instruction ) |
| CCMPr32-encode | ( Rm cond4 Rn nzcv4 -- instruction ) |
| CCMPr64-encode | ( Rm cond4 Rn nzcv4 -- instruction ) |
| CFINV-encode | ( -- instruction ) |
| CFP-encode | ( Rt -- instruction ) |
| CINC32-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CINC64-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CINV32-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CINV64-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CLREX-encode | ( CRm -- instruction ) |
| CLS32-encode | ( Rn Rd -- instruction ) |
| CLS64-encode | ( Rn Rd -- instruction ) |
| CLZ32-encode | ( Rn Rd -- instruction ) |
| CLZ64-encode | ( Rn Rd -- instruction ) |
| CMN-sr32-encode | ( shift2 Rm imm6 Rn -- instruction ) |
| CMN-sr64-encode | ( shift2 Rm imm6 Rn -- instruction ) |
| CMNer32-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| CMNer64-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| CMNi32-encode | ( shift2 imm12 Rn -- instruction ) |
| CMNi64-encode | ( shift2 imm12 Rn -- instruction ) |
| CMPP-encode | ( Xm Xn Xd -- instruction ) |
| CMPer32-encode | ( Rm option3 imm3 Rn -- instruction ) |
| CMPer64-encode | ( Rm option3 imm3 Rn -- instruction ) |
| CMPi32-encode | ( shift2 imm12 Rn -- instruction ) |
| CMPi64-encode | ( shift2 imm12 Rn -- instruction ) |
| CMPsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| CMPsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| CNEG32-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CNEG64-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CPP-encode | ( Rt -- instruction ) |
| CRC32B32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32B64-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CB32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CB64-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CH32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CH64-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CW32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CW64-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CX32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32CX64-encode | ( Rm Rn Rd -- instruction ) |
| CRC32H32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32H64-encode | ( Rm Rn Rd -- instruction ) |
| CRC32W32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32W64-encode | ( Rm Rn Rd -- instruction ) |
| CRC32X32-encode | ( Rm Rn Rd -- instruction ) |
| CRC32X64-encode | ( Rm Rn Rd -- instruction ) |
| CRm | ( n -- n ) |
| CRm-range | ( value -- * ) |
| CRm4 | ( n -- n ) |
| CRm4-range | ( value -- * ) |
| CRn | ( n -- n ) |
| CRn-range | ( value -- * ) |
| CRn4 | ( n -- n ) |
| CRn4-range | ( value -- * ) |
| CS | ( -- n ) |
| CSDB-encode | ( -- instruction ) |
| CSEL32-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CSEL64-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CSET32-encode | ( cond4 Rd -- instruction ) |
| CSET64-encode | ( cond4 Rd -- instruction ) |
| CSETM32-encode | ( cond4 Rd -- instruction ) |
| CSETM64-encode | ( cond4 Rd -- instruction ) |
| CSINC32-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CSINC64-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CSINV32-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CSINV64-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CSNEG32-encode | ( Rm cond4 Rn Rd -- instruction ) |
| CSNEG64-encode | ( Rm cond4 Rn Rd -- instruction ) |
| D | ( n -- n ) |
| D-range | ( value -- * ) |
| DC-encode | ( op3 CRm op3 Rt -- instruction ) |
| DCPS1-encode | ( imm16 -- instruction ) |
| DCPS2-encode | ( imm16 -- instruction ) |
| DCPS3-encode | ( imm16 -- instruction ) |
| DMB-encode | ( CRm -- instruction ) |
| DPRS-encode | ( -- instruction ) |
| DSB-encode | ( CRm -- instruction ) |
| DVP-encode | ( Rt -- instruction ) |
| EONsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| EONsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| EORi32-encode | ( immrimms Rn Rd -- instruction ) |
| EORi64-encode | ( Nimmrimms Rn Rd -- instruction ) |
| EORsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| EORsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| EQ | ( -- n ) |
| ERET-encode | ( -- instruction ) |
| ERETAA-encode | ( -- instruction ) |
| ERETAB-encode | ( -- instruction ) |
| ESB-encode | ( -- instruction ) |
| EXTR32-encode | ( Rm imms Rn Rd -- instruction ) |
| EXTR64-encode | ( Rm imms Rn Rd -- instruction ) |
| GE | ( -- n ) |
| GMI-encode | ( Xm Xn Xd -- instruction ) |
| GT | ( -- n ) |
| HI | ( -- n ) |
| HINT-encode | ( CRm op3 -- instruction ) |
| HLT-encode | ( imm16 -- instruction ) |
| HS | ( -- n ) |
| HVC-encode | ( imm16 -- instruction ) |
| IC-encode | ( op3 CRm op3 Rt -- instruction ) |
| IRG-encode | ( Xm Xn Xd -- instruction ) |
| ISB-encode | ( CRm -- instruction ) |
| L | ( n -- n ) |
| L-range | ( value -- * ) |
| LDADD32-encode | ( Rs Rn Rt -- instruction ) |
| LDADD64-encode | ( Rs Rn Rt -- instruction ) |
| LDADDA32-encode | ( Rs Rn Rt -- instruction ) |
| LDADDA64-encode | ( Rs Rn Rt -- instruction ) |
| LDADDAB-encode | ( Rs Rn Rt -- instruction ) |
| LDADDAH-encode | ( Rs Rn Rt -- instruction ) |
| LDADDAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDADDAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDADDALB-encode | ( Rs Rn Rt -- instruction ) |
| LDADDALH-encode | ( Rs Rn Rt -- instruction ) |
| LDADDB-encode | ( Rs Rn Rt -- instruction ) |
| LDADDH-encode | ( Rs Rn Rt -- instruction ) |
| LDADDL32-encode | ( Rs Rn Rt -- instruction ) |
| LDADDL64-encode | ( Rs Rn Rt -- instruction ) |
| LDADDLB-encode | ( Rs Rn Rt -- instruction ) |
| LDADDLH-encode | ( Rs Rn Rt -- instruction ) |
| LDAPR32-encode | ( Rn Rt -- instruction ) |
| LDAPR64-encode | ( Rn Rt -- instruction ) |
| LDAPRB-encode | ( Rn Rt -- instruction ) |
| LDAPRH-encode | ( Rn Rt -- instruction ) |
| LDAPUR32-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPUR64-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPURB-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPURH-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPURSB32-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPURSB64-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPURSH32-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPURSH64-encode | ( imm9 Rn Rt -- instruction ) |
| LDAPURSW-encode | ( imm9 Rn Rt -- instruction ) |
| LDAR32-encode | ( Rn Rt -- instruction ) |
| LDAR64-encode | ( Rn Rt -- instruction ) |
| LDARB-encode | ( Rn Rt -- instruction ) |
| LDARH-encode | ( Rn Rt -- instruction ) |
| LDAXP32-encode | ( Rt2 Rn Rt -- instruction ) |
| LDAXP64-encode | ( Rt2 Rn Rt -- instruction ) |
| LDAXR32-encode | ( Rn Rt -- instruction ) |
| LDAXR64-encode | ( Rn Rt -- instruction ) |
| LDAXRB-encode | ( Rn Rt -- instruction ) |
| LDAXRH-encode | ( Rn Rt -- instruction ) |
| LDCLR32-encode | ( Rs Rn Rt -- instruction ) |
| LDCLR64-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRA-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRA32-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRA64-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRAB-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRAH-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRALB-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRALH-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRB-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRL32-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRL64-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRLB-encode | ( Rs Rn Rt -- instruction ) |
| LDCLRLH-encode | ( Rs Rn Rt -- instruction ) |
| LDEOR32-encode | ( Rs Rn Rt -- instruction ) |
| LDEOR64-encode | ( Rs Rn Rt -- instruction ) |
| LDEORA32-encode | ( Rs Rn Rt -- instruction ) |
| LDEORA64-encode | ( Rs Rn Rt -- instruction ) |
| LDEORAB-encode | ( Rs Rn Rt -- instruction ) |
| LDEORAH-encode | ( Rs Rn Rt -- instruction ) |
| LDEORAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDEORAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDEORALB-encode | ( Rs Rn Rt -- instruction ) |
| LDEORALH-encode | ( Rs Rn Rt -- instruction ) |
| LDEORB-encode | ( Rs Rn Rt -- instruction ) |
| LDEORH-encode | ( Rs Rn Rt -- instruction ) |
| LDEORL32-encode | ( Rs Rn Rt -- instruction ) |
| LDEORL64-encode | ( Rs Rn Rt -- instruction ) |
| LDEORLB-encode | ( Rs Rn Rt -- instruction ) |
| LDEORLH-encode | ( Rs Rn Rt -- instruction ) |
| LDG-encode | ( imm9 Xn Xt -- instruction ) |
| LDGV-encode | ( Xn Xt -- instruction ) |
| LDLAR32-encode | ( Rn Rt -- instruction ) |
| LDLAR64-encode | ( Rn Rt -- instruction ) |
| LDLARB-encode | ( Rn Rt -- instruction ) |
| LDLARH-encode | ( Rn Rt -- instruction ) |
| LDNP32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDNP64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPSWpost32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPSWpost64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPSWpre32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPSWpre64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPSWsoff32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPSWsoff64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPpost32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPpost64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPpre32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPpre64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPsoff32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDPsoff64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| LDRAAoff-encode | ( S imm9 Rn Rt -- instruction ) |
| LDRAApre-encode | ( S imm9 Rn Rt -- instruction ) |
| LDRABoff-encode | ( S imm9 Rn Rt -- instruction ) |
| LDRABpre-encode | ( S imm9 Rn Rt -- instruction ) |
| LDRBimmpost-encode | ( imm9 Rn Rt -- instruction ) |
| LDRBimmpre-encode | ( imm9 Rn Rt -- instruction ) |
| LDRBimmuoff-encode | ( imm12 Rn Rt -- instruction ) |
| LDRBrext-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRBrshift-encode | ( Rm S Rn Rt -- instruction ) |
| LDRHimmpost-encode | ( imm9 Rn Rt -- instruction ) |
| LDRHimmpre-encode | ( imm9 Rn Rt -- instruction ) |
| LDRHimmuoff-encode | ( imm12 Rn Rt -- instruction ) |
| LDRHr-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRSBextreg32-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRSBextreg64-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRSBimmpost32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSBimmpost64-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSBimmpre32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSBimmpre64-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSBimmuoff32-encode | ( imm12 Rn Rt -- instruction ) |
| LDRSBimmuoff64-encode | ( imm12 Rn Rt -- instruction ) |
| LDRSBshiftreg32-encode | ( Rm S Rn Rt -- instruction ) |
| LDRSBshiftreg64-encode | ( Rm S Rn Rt -- instruction ) |
| LDRSH32-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRSH64-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRSHimmpost32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSHimmpost64-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSHimmpre32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSHimmpre64-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSHimmuoff32-encode | ( imm12 Rn Rt -- instruction ) |
| LDRSHimmuoff64-encode | ( imm12 Rn Rt -- instruction ) |
| LDRSWimmpost32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSWimmpre32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRSWimmuoff64-encode | ( imm12 Rn Rt -- instruction ) |
| LDRSWl-encode | ( imm19 Rt -- instruction ) |
| LDRSWr-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRl32-encode | ( imm19 Rt -- instruction ) |
| LDRl64-encode | ( imm19 Rt -- instruction ) |
| LDRpost32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRpost64-encode | ( imm9 Rn Rt -- instruction ) |
| LDRpre32-encode | ( imm9 Rn Rt -- instruction ) |
| LDRpre64-encode | ( imm9 Rn Rt -- instruction ) |
| LDRr32-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRr64-encode | ( Rm option3 S Rn Rt -- instruction ) |
| LDRuoff32-encode | ( imm12 Rn Rt -- instruction ) |
| LDRuoff64-encode | ( imm12 Rn Rt -- instruction ) |
| LDSET32-encode | ( Rs Rn Rt -- instruction ) |
| LDSET64-encode | ( Rs Rn Rt -- instruction ) |
| LDSETA32-encode | ( Rs Rn Rt -- instruction ) |
| LDSETA64-encode | ( Rs Rn Rt -- instruction ) |
| LDSETAB-encode | ( Rs Rn Rt -- instruction ) |
| LDSETAH-encode | ( Rs Rn Rt -- instruction ) |
| LDSETAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDSETAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDSETALB-encode | ( Rs Rn Rt -- instruction ) |
| LDSETALH-encode | ( Rs Rn Rt -- instruction ) |
| LDSETB-encode | ( Rs Rn Rt -- instruction ) |
| LDSETH-encode | ( Rs Rn Rt -- instruction ) |
| LDSETL32-encode | ( Rs Rn Rt -- instruction ) |
| LDSETL64-encode | ( Rs Rn Rt -- instruction ) |
| LDSETLB-encode | ( Rs Rn Rt -- instruction ) |
| LDSETLH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAX32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAX64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXA32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXA64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXAB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXAH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXALB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXALH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXL32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXL64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXLB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMAXLH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMIN32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMIN64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINA32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINA64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINAB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINAH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINALB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINALH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINH-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINL32-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINL64-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINLB-encode | ( Rs Rn Rt -- instruction ) |
| LDSMINLH-encode | ( Rs Rn Rt -- instruction ) |
| LDTR32-encode | ( imm9 Rn Rt -- instruction ) |
| LDTR64-encode | ( imm9 Rn Rt -- instruction ) |
| LDTRB-encode | ( imm9 Rn Rt -- instruction ) |
| LDTRH-encode | ( imm9 Rn Rt -- instruction ) |
| LDTRSB32-encode | ( imm9 Rn Rt -- instruction ) |
| LDTRSB64-encode | ( imm9 Rn Rt -- instruction ) |
| LDTRSH32-encode | ( imm9 Rn Rt -- instruction ) |
| LDTRSH64-encode | ( imm9 Rn Rt -- instruction ) |
| LDTRSW-encode | ( imm9 Rn Rt -- instruction ) |
| LDUMAX32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAX64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXA32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXA64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXAB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXAH-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXALB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXALH-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXH-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXL32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXL64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXLB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMAXLH-encode | ( Rs Rn Rt -- instruction ) |
| LDUMIN32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMIN64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINA32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINA64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINAB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINAH-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINAL32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINAL64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINALB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINALH-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINH-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINL32-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINL64-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINLB-encode | ( Rs Rn Rt -- instruction ) |
| LDUMINLH-encode | ( Rs Rn Rt -- instruction ) |
| LDUR32-encode | ( imm9 Rn Rt -- instruction ) |
| LDUR64-encode | ( imm9 Rn Rt -- instruction ) |
| LDURB-encode | ( imm9 Rn Rt -- instruction ) |
| LDURH-encode | ( imm9 Rn Rt -- instruction ) |
| LDURSB32-encode | ( imm9 Rn Rt -- instruction ) |
| LDURSB64-encode | ( imm9 Rn Rt -- instruction ) |
| LDURSH32-encode | ( imm9 Rn Rt -- instruction ) |
| LDURSH64-encode | ( imm9 Rn Rt -- instruction ) |
| LDURSW-encode | ( imm9 Rn Rt -- instruction ) |
| LDXP32-encode | ( Rt2 Rn Rt -- instruction ) |
| LDXP64-encode | ( Rt2 Rn Rt -- instruction ) |
| LDXR32-encode | ( Rn Rt -- instruction ) |
| LDXR64-encode | ( Rn Rt -- instruction ) |
| LDXRB-encode | ( Rn Rt -- instruction ) |
| LDXRH-encode | ( Rn Rt -- instruction ) |
| LE | ( -- n ) |
| LO | ( -- n ) |
| LS | ( -- n ) |
| LSLV32-encode | ( Rm Rn Rd -- instruction ) |
| LSLV64-encode | ( Rm Rn Rd -- instruction ) |
| LSLi32-encode | ( immrimms Rn Rd -- instruction ) |
| LSLi64-encode | ( immrimms Rn Rd -- instruction ) |
| LSLr32-encode | ( Rm Rn Rd -- instruction ) |
| LSLr64-encode | ( Rm Rn Rd -- instruction ) |
| LSRV32-encode | ( Rm Rn Rd -- instruction ) |
| LSRV64-encode | ( Rm Rn Rd -- instruction ) |
| LSRi32-encode | ( immr Rn Rd -- instruction ) |
| LSRi64-encode | ( immr Rn Rd -- instruction ) |
| LSRr32-encode | ( Rm Rn Rd -- instruction ) |
| LSRr64-encode | ( Rm Rn Rd -- instruction ) |
| LT | ( -- n ) |
| M | ( n -- n ) |
| M-range | ( value -- * ) |
| MADD32-encode | ( Rm Ra Rn Rd -- instruction ) |
| MADD64-encode | ( Rm Ra Rn Rd -- instruction ) |
| MI | ( -- n ) |
| MNEG32-encode | ( Rm Rn Rd -- instruction ) |
| MNEG64-encode | ( Rm Rn Rd -- instruction ) |
| MOVK32-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVK64-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVN32-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVN64-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVZ32-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVZ64-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVbi32-encode | ( immr imms Rn -- instruction ) |
| MOVbi64-encode | ( Nimmrimms Rn -- instruction ) |
| MOViwi32-encode | ( hw2 imm16 Rd -- instruction ) |
| MOViwi64-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVr32-encode | ( Rm Rd -- instruction ) |
| MOVr64-encode | ( Rm Rd -- instruction ) |
| MOVsp32-encode | ( shift2 Rn Rd -- instruction ) |
| MOVsp64-encode | ( shift2 Rn Rd -- instruction ) |
| MOVwi32-encode | ( hw2 imm16 Rd -- instruction ) |
| MOVwi64-encode | ( hw2 imm16 Rd -- instruction ) |
| MRS-encode | ( o0 op3 CRn CRm op3 Rt -- instruction ) |
| MRSi-encode | ( op3 CRm op3 -- instruction ) |
| MRSr-encode | ( o0 op3 CRn CRm op3 Rt -- instruction ) |
| MSUB32-encode | ( Rm Ra Rn Rd -- instruction ) |
| MSUB64-encode | ( Rm Ra Rn Rd -- instruction ) |
| MUL32-encode | ( Rm Rn Rd -- instruction ) |
| MUL64-encode | ( Rm Rn Rd -- instruction ) |
| MVN32-encode | ( shift2 Rm imm6 Rd -- instruction ) |
| MVN64-encode | ( shift2 Rm imm6 Rd -- instruction ) |
| N | ( n -- n ) |
| N-range | ( value -- * ) |
| NE | ( -- n ) |
| NEGS32-encode | ( shift2 Rm imm6 Rd -- instruction ) |
| NEGS64-encode | ( shift2 Rm imm6 Rd -- instruction ) |
| NEGsr32-encode | ( shift2 Rm imm6 Rd -- instruction ) |
| NEGsr64-encode | ( shift2 Rm imm6 Rd -- instruction ) |
| NGC32-encode | ( Rm Rd -- instruction ) |
| NGC64-encode | ( Rm Rd -- instruction ) |
| NGCS32-encode | ( Rm Rd -- instruction ) |
| NGCS64-encode | ( Rm Rd -- instruction ) |
| NOP | ( -- instruction ) |
| NV | ( -- n ) |
| Nimmrimms | ( n -- n ) |
| Nimmrimms-range | ( value -- * ) |
| ORNsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ORNsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ORR32-encode | ( immrimms Rn Rd -- instruction ) |
| ORR64-encode | ( Nimmrimms Rn Rd -- instruction ) |
| ORRsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| ORRsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| PACDA-encode | ( Rn Rd -- instruction ) |
| PACDB-encode | ( Rn Rd -- instruction ) |
| PACDZA-encode | ( Rd -- instruction ) |
| PACDZB-encode | ( Rd -- instruction ) |
| PACGA-encode | ( Rm Rn Rd -- instruction ) |
| PACIA-encode | ( Rn Rd -- instruction ) |
| PACIA1716-encode | ( -- instruction ) |
| PACIASP-encode | ( -- instruction ) |
| PACIAZ-encode | ( -- instruction ) |
| PACIB-encode | ( Rn Rd -- instruction ) |
| PACIB1716-encode | ( -- instruction ) |
| PACIBSP-encode | ( -- instruction ) |
| PACIBZ-encode | ( -- instruction ) |
| PACIZA-encode | ( Rn Rd -- instruction ) |
| PACIZB-encode | ( Rn Rd -- instruction ) |
| PL | ( -- n ) |
| PRFMi-encode | ( imm12 Rn Rt -- instruction ) |
| PRFMl-encode | ( imm19 Rt -- instruction ) |
| PRFMr-encode | ( Rm option3 S Rn Rt -- instruction ) |
| PRFMunscoff-encode | ( imm9 Rn Rt -- instruction ) |
| PSB-CSYNC-encode | ( -- instruction ) |
| PSSBB-encode | ( -- instruction ) |
| Q | ( n -- n ) |
| Q-range | ( value -- * ) |
| RBIT32-encode | ( Rn Rd -- instruction ) |
| RBIT64-encode | ( Rn Rd -- instruction ) |
| RET-encode | ( Rn -- instruction ) |
| RETAA-encode | ( -- instruction ) |
| RETAB-encode | ( -- instruction ) |
| REV16_32 | ( Rn Rd -- instruction ) |
| REV16_64 | ( Rn Rd -- instruction ) |
| REV32-encode | ( Rn Rd -- instruction ) |
| REV64-encode | ( Q size2 Rn Rd -- instruction ) |
| REVb32-encode | ( Rn Rd -- instruction ) |
| REVb64-encode | ( Rn Rd -- instruction ) |
| RMIF-encode | ( imm6 Rn mask4 -- instruction ) |
| RORV32-encode | ( Rm Rn Rd -- instruction ) |
| RORV64-encode | ( Rm Rn Rd -- instruction ) |
| RORi32-encode | ( Rm imm5 Rn Rd -- instruction ) |
| RORi64-encode | ( Rm imms Rn Rd -- instruction ) |
| RORr32-encode | ( Rm Rn Rd -- instruction ) |
| RORr64-encode | ( Rm Rn Rd -- instruction ) |
| Ra | ( n -- n ) |
| Ra-range | ( value -- * ) |
| Rd | ( n -- n ) |
| Rd-range | ( value -- * ) |
| Rm | ( n -- n ) |
| Rm-range | ( value -- * ) |
| Rn | ( n -- n ) |
| Rn-range | ( value -- * ) |
| Rs | ( n -- n ) |
| Rs-range | ( value -- * ) |
| Rt | ( n -- n ) |
| Rt-range | ( value -- * ) |
| Rt2 | ( n -- n ) |
| Rt2-range | ( value -- * ) |
| S | ( n -- n ) |
| S-range | ( value -- * ) |
| SB-encode | ( -- instruction ) |
| SBC32-encode | ( Rm Rn Rd -- instruction ) |
| SBC64-encode | ( Rm Rn Rd -- instruction ) |
| SBCS32-encode | ( Rm Rn Rd -- instruction ) |
| SBCS64-encode | ( Rm Rn Rd -- instruction ) |
| SBFIZ32-encode | ( immr imms Rn Rd -- instruction ) |
| SBFIZ64-encode | ( immr imms Rn Rd -- instruction ) |
| SBFM32-encode | ( immr imms Rn Rd -- instruction ) |
| SBFM64-encode | ( immr imms Rn Rd -- instruction ) |
| SBFX32-encode | ( immr imms Rn Rd -- instruction ) |
| SBFX64-encode | ( immr imms Rn Rd -- instruction ) |
| SDIV32-encode | ( Rm Rn Rd -- instruction ) |
| SDIV64-encode | ( Rm Rn Rd -- instruction ) |
| SETF16-encode | ( Rn -- instruction ) |
| SETF8-encode | ( Rn -- instruction ) |
| SEV-encode | ( -- instruction ) |
| SEVL-encode | ( -- instruction ) |
| SMADDL-encode | ( Rm Ra Rn Rd -- instruction ) |
| SMC-encode | ( imm16 -- instruction ) |
| SMNEGL-encode | ( Rm Rn Rd -- instruction ) |
| SMSUBL-encode | ( Rm Ra Rn Rd -- instruction ) |
| SMULH-encode | ( Rm Rn Rd -- instruction ) |
| SMULL-encode | ( Rm Rn Rd -- instruction ) |
 SP | ( -- value ) |
| SSBB-encode | ( -- instruction ) |
| ST2Gpost-encode | ( imm9 Xn -- instruction ) |
| ST2Gpre-encode | ( imm9 Xn -- instruction ) |
| ST2Gsoff-encode | ( imm9 Xn -- instruction ) |
| STADD32-encode | ( Rs Rn -- instruction ) |
| STADD64-encode | ( Rs Rn -- instruction ) |
| STADDB-encode | ( Rs Rn -- instruction ) |
| STADDH-encode | ( Rs Rn -- instruction ) |
| STADDL32-encode | ( Rs Rn -- instruction ) |
| STADDL64-encode | ( Rs Rn -- instruction ) |
| STADDLB-encode | ( Rs Rn -- instruction ) |
| STADDLH-encode | ( Rs Rn -- instruction ) |
| STCLR32-encode | ( Rs Rn -- instruction ) |
| STCLR64-encode | ( Rs Rn -- instruction ) |
| STCLRB-encode | ( Rs Rn -- instruction ) |
| STCLRH-encode | ( Rs Rn -- instruction ) |
| STCLRL32-encode | ( Rs Rn -- instruction ) |
| STCLRL64-encode | ( Rs Rn -- instruction ) |
| STCLRLB-encode | ( Rs Rn -- instruction ) |
| STCLRLH-encode | ( Rs Rn -- instruction ) |
| STEOR32-encode | ( Rs Rn -- instruction ) |
| STEOR64-encode | ( Rs Rn -- instruction ) |
| STEORB-encode | ( Rs Rn -- instruction ) |
| STEORH-encode | ( Rs Rn -- instruction ) |
| STEORL32-encode | ( Rs Rn -- instruction ) |
| STEORL64-encode | ( Rs Rn -- instruction ) |
| STEORLB-encode | ( Rs Rn -- instruction ) |
| STEORLH-encode | ( Rs Rn -- instruction ) |
| STGPpost-encode | ( simm7 Xt2 Xn Xt -- instruction ) |
| STGPpre-encode | ( simm7 Xt2 Xn Xt -- instruction ) |
| STGPsoff-encode | ( simm7 Xt2 Xn Xt -- instruction ) |
| STGV-encode | ( Xn Xt -- instruction ) |
| STGpost-encode | ( imm9 Xn -- instruction ) |
| STGpre-encode | ( imm9 Xn -- instruction ) |
| STGsoff-encode | ( imm9 Xn -- instruction ) |
| STLLR32-encode | ( Rn Rt -- instruction ) |
| STLLR64-encode | ( Rn Rt -- instruction ) |
| STLLRB-encode | ( Rn Rt -- instruction ) |
| STLLRH-encode | ( Rn Rt -- instruction ) |
| STLR32-encode | ( Rn Rt -- instruction ) |
| STLR64-encode | ( Rn Rt -- instruction ) |
| STLRB-encode | ( Rn Rt -- instruction ) |
| STLRH-encode | ( Rn Rt -- instruction ) |
| STLUR32-encode | ( imm9 Rn Rt -- instruction ) |
| STLUR64-encode | ( imm9 Rn Rt -- instruction ) |
| STLURB-encode | ( imm9 Rn Rt -- instruction ) |
| STLURH-encode | ( imm9 Rn Rt -- instruction ) |
| STLXP32-encode | ( Rs Rt2 Rn Rt -- instruction ) |
| STLXP64-encode | ( Rs Rt2 Rn Rt -- instruction ) |
| STLXR32-encode | ( Rs Rn Rt -- instruction ) |
| STLXR64-encode | ( Rs Rn Rt -- instruction ) |
| STLXRB-encode | ( Rs Rn Rt -- instruction ) |
| STLXRH-encode | ( Rs Rn Rt -- instruction ) |
| STNP32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STNP64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STPpost32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STPpost64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STPpre32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STPpre64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STPsoff32-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STPsoff64-encode | ( imm7 Rt2 Rn Rt -- instruction ) |
| STRBext-encode | ( Rm option3 S Rn Rt -- instruction ) |
| STRBshift-encode | ( Rm S Rn Rt -- instruction ) |
| STRH-encode | ( Rm option3 S Rn Rt -- instruction ) |
| STRHpost-encode | ( imm9 Rn Rt -- instruction ) |
| STRHpre-encode | ( imm9 Rn Rt -- instruction ) |
| STRHuoff-encode | ( imm12 Rn Rt -- instruction ) |
| STRpost-encode | ( imm9 Rn Rt -- instruction ) |
| STRpost32-encode | ( imm9 Rn Rt -- instruction ) |
| STRpost64-encode | ( imm9 Rn Rt -- instruction ) |
| STRpre-encode | ( imm9 Rn Rt -- instruction ) |
| STRpre32-encode | ( imm9 Rn Rt -- instruction ) |
| STRpre64-encode | ( imm9 Rn Rt -- instruction ) |
| STRr32-encode | ( Rm option3 S Rn Rt -- instruction ) |
| STRr64-encode | ( Rm option3 S Rn Rt -- instruction ) |
| STRuoff-encode | ( imm12 Rn Rt -- instruction ) |
| STRuoff32-encode | ( imm12 Rn Rt -- instruction ) |
| STRuoff64-encode | ( imm12 Rn Rt -- instruction ) |
| STSET32-encode | ( Rs Rn -- instruction ) |
| STSET64-encode | ( Rs Rn -- instruction ) |
| STSETB-encode | ( Rs Rn -- instruction ) |
| STSETH-encode | ( Rs Rn -- instruction ) |
| STSETL32-encode | ( Rs Rn -- instruction ) |
| STSETL64-encode | ( Rs Rn -- instruction ) |
| STSETLB-encode | ( Rs Rn -- instruction ) |
| STSETLH-encode | ( Rs Rn -- instruction ) |
| STSMAX32-encode | ( Rs Rn -- instruction ) |
| STSMAX64-encode | ( Rs Rn -- instruction ) |
| STSMAXB-encode | ( Rs Rn -- instruction ) |
| STSMAXH-encode | ( Rs Rn -- instruction ) |
| STSMAXL32-encode | ( Rs Rn -- instruction ) |
| STSMAXL64-encode | ( Rs Rn -- instruction ) |
| STSMAXLB-encode | ( Rs Rn -- instruction ) |
| STSMAXLH-encode | ( Rs Rn -- instruction ) |
| STSMIN32-encode | ( Rs Rn -- instruction ) |
| STSMIN64-encode | ( Rs Rn -- instruction ) |
| STSMINB-encode | ( Rs Rn -- instruction ) |
| STSMINH-encode | ( Rs Rn -- instruction ) |
| STSMINL32-encode | ( Rs Rn -- instruction ) |
| STSMINL64-encode | ( Rs Rn -- instruction ) |
| STSMINLB-encode | ( Rs Rn -- instruction ) |
| STSMINLH-encode | ( Rs Rn -- instruction ) |
| STTR32-encode | ( imm9 Rn Rt -- instruction ) |
| STTR64-encode | ( imm9 Rn Rt -- instruction ) |
| STTRB-encode | ( imm9 Rn Rt -- instruction ) |
| STTRH-encode | ( imm9 Rn Rt -- instruction ) |
| STUMAX32-encode | ( Rs Rn -- instruction ) |
| STUMAX64-encode | ( Rs Rn -- instruction ) |
| STUMAXB-encode | ( Rs Rn -- instruction ) |
| STUMAXH-encode | ( Rs Rn -- instruction ) |
| STUMAXL32-encode | ( Rs Rn -- instruction ) |
| STUMAXL64-encode | ( Rs Rn -- instruction ) |
| STUMAXLB-encode | ( Rs Rn -- instruction ) |
| STUMAXLH-encode | ( Rs Rn -- instruction ) |
| STUMIN32-encode | ( Rs Rn -- instruction ) |
| STUMIN64-encode | ( Rs Rn -- instruction ) |
| STUMINB-encode | ( Rs Rn -- instruction ) |
| STUMINH-encode | ( Rs Rn -- instruction ) |
| STUMINL32-encode | ( Rs Rn -- instruction ) |
| STUMINL64-encode | ( Rs Rn -- instruction ) |
| STUMINLB-encode | ( Rs Rn -- instruction ) |
| STUMINLH-encode | ( Rs Rn -- instruction ) |
| STUR32-encode | ( imm9 Rn Rt -- instruction ) |
| STUR64-encode | ( imm9 Rn Rt -- instruction ) |
| STURB-encode | ( imm9 Rn Rt -- instruction ) |
| STURH-encode | ( imm9 Rn Rt -- instruction ) |
| STXP32-encode | ( Rs Rt2 Rn Rt -- instruction ) |
| STXP64-encode | ( Rs Rt2 Rn Rt -- instruction ) |
| STXR32-encode | ( Rs Rn Rt -- instruction ) |
| STXR64-encode | ( Rs Rn Rt -- instruction ) |
| STXRB-encode | ( Rs Rn Rt -- instruction ) |
| STXRH-encode | ( Rs Rn Rt -- instruction ) |
| STZ2Gpost-encode | ( imm9 Xn -- instruction ) |
| STZ2Gpre-encode | ( imm9 Xn -- instruction ) |
| STZ2Gsoff-encode | ( imm9 Xn -- instruction ) |
| STZGpost-encode | ( imm9 Xn -- instruction ) |
| STZGpre-encode | ( imm9 Xn -- instruction ) |
| STZGsoff-encode | ( imm9 Xn -- instruction ) |
| SUBG-encode | ( uimm6 uimm4 Xn Xd -- instruction ) |
| SUBP-encode | ( Xm Xn Xd -- instruction ) |
| SUBPS-encode | ( Xm Xn Xd -- instruction ) |
| SUBSer32-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| SUBSer64-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| SUBSimm32-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| SUBSimm64-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| SUBSsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| SUBSsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| SUBer32-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| SUBer64-encode | ( Rm option3 imm3 Rn Rd -- instruction ) |
| SUBi32-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| SUBi64-encode | ( shift2 imm12 Rn Rd -- instruction ) |
| SUBsr32-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| SUBsr64-encode | ( shift2 Rm imm6 Rn Rd -- instruction ) |
| SVC-encode | ( imm16 -- instruction ) |
| SWP32-encode | ( Rs Rn Rt -- instruction ) |
| SWP64-encode | ( Rs Rn Rt -- instruction ) |
| SWPA32-encode | ( Rs Rn Rt -- instruction ) |
| SWPA64-encode | ( Rs Rn Rt -- instruction ) |
| SWPAB-encode | ( Rs Rn Rt -- instruction ) |
| SWPAH-encode | ( Rs Rn Rt -- instruction ) |
| SWPAL32-encode | ( Rs Rn Rt -- instruction ) |
| SWPAL64-encode | ( Rs Rn Rt -- instruction ) |
| SWPALB-encode | ( Rs Rn Rt -- instruction ) |
| SWPALH-encode | ( Rs Rn Rt -- instruction ) |
| SWPB-encode | ( Rs Rn Rt -- instruction ) |
| SWPH-encode | ( Rs Rn Rt -- instruction ) |
| SWPL32-encode | ( Rs Rn Rt -- instruction ) |
| SWPL64-encode | ( Rs Rn Rt -- instruction ) |
| SWPLB-encode | ( Rs Rn Rt -- instruction ) |
| SWPLH-encode | ( Rs Rn Rt -- instruction ) |
| SXTB32-encode | ( Rn Rd -- instruction ) |
| SXTB64-encode | ( Rn Rd -- instruction ) |
| SXTH32-encode | ( Rn Rd -- instruction ) |
| SXTH64-encode | ( Rn Rd -- instruction ) |
| SXTW-encode | ( Rn Rd -- instruction ) |
| SYS-encode | ( op3 CRn CRm op3 Rt -- instruction ) |
| SYSL-encode | ( op3 CRn CRm op3 Rt -- instruction ) |
| TBHZW-encode | ( b40 imm14 Rt -- instruction ) |
| TBHZX-encode | ( b40 imm14 Rt -- instruction ) |
| TBNZW-encode | ( b40 imm14 Rt -- instruction ) |
| TBNZX-encode | ( b40 imm14 Rt -- instruction ) |
| TLBI-encode | ( op3 CRm op3 Rt -- instruction ) |
| TSB-CSYNC-encode | ( -- instruction ) |
| TSTi32-encode | ( immrimms Rn -- instruction ) |
| TSTi64-encode | ( Nimmrimms Rn -- instruction ) |
| TSTsr32-encode | ( shift2 Rm imm6 Rn -- instruction ) |
| TSTsr64-encode | ( shift2 Rm imm6 Rn -- instruction ) |
| U | ( n -- n ) |
| U-range | ( value -- * ) |
| UBFIZ32-encode | ( immr imms Rn Rd -- instruction ) |
| UBFIZ64-encode | ( immr imms Rn Rd -- instruction ) |
| UBFM32-encode | ( immr imms Rn Rd -- instruction ) |
| UBFM64-encode | ( immr imms Rn Rd -- instruction ) |
| UBFX32-encode | ( immr imms Rn Rd -- instruction ) |
| UBFX64-encode | ( immr imms Rn Rd -- instruction ) |
| UDF-encode | ( imm16 -- instruction ) |
| UDIV32-encode | ( Rm Rn Rd -- instruction ) |
| UDIV64-encode | ( Rm Rn Rd -- instruction ) |
| UMADDL-encode | ( Rm Ra Rn Rd -- instruction ) |
| UMNEGL-encode | ( Rm Rn Rd -- instruction ) |
| UMSUBL-encode | ( Rm Ra Rn Rd -- instruction ) |
| UMULH-encode | ( Rm Rn Rd -- instruction ) |
| UMULL-encode | ( Rm Rn Rd -- instruction ) |
| UXTB-encode | ( Rn Rd -- instruction ) |
| UXTH-encode | ( Rn Rd -- instruction ) |
| VC | ( -- n ) |
| VS | ( -- n ) |
| WFE-encode | ( -- instruction ) |
| WFI-encode | ( -- instruction ) |
| WSP | ( -- value ) |
| WZR | ( -- value ) |
| XAFlag-encode | ( -- instruction ) |
| XPACD-encode | ( Rd -- instruction ) |
| XPACI-encode | ( Rd -- instruction ) |
| XPACLRI-encode | ( -- instruction ) |
| XZR | ( -- value ) |
| Xd | ( n -- n ) |
| Xd-range | ( value -- * ) |
| Xm | ( n -- n ) |
| Xm-range | ( value -- * ) |
| Xn | ( n -- n ) |
| Xn-range | ( value -- * ) |
| Xt | ( n -- n ) |
| Xt-range | ( value -- * ) |
| Xt2 | ( n -- n ) |
| Xt2-range | ( value -- * ) |
| YIELD-encode | ( -- instruction ) |
| Z | ( n -- n ) |
| Z-range | ( value -- * ) |
| a1 | ( n -- n ) |
| a1-range | ( value -- * ) |
| arm-bitfield | ( seq -- assoc ) |
| b1 | ( n -- n ) |
| b1-range | ( value -- * ) |
| b40 | ( n -- n ) |
| b40-range | ( value -- * ) |
| bad-instruction | ( values -- * ) |
| c1 | ( n -- n ) |
| c1-range | ( value -- * ) |
| cmode4 | ( n -- n ) |
| cmode4-range | ( value -- * ) |
| cond4 | ( n -- n ) |
| cond4-range | ( value -- * ) |
| d1 | ( n -- n ) |
| d1-range | ( value -- * ) |
| e1 | ( n -- n ) |
| e1-range | ( value -- * ) |
| error-word | ( word -- new-class ) |
| f1 | ( n -- n ) |
| f1-range | ( value -- * ) |
| g1 | ( n -- n ) |
| g1-range | ( value -- * ) |
| h1 | ( n -- n ) |
| h1-range | ( value -- * ) |
| hw2 | ( n -- n ) |
| hw2-range | ( value -- * ) |
| imm12 | ( n -- n ) |
| imm12-range | ( value -- * ) |
| imm12>parts-32 | ( imm12 -- imms immr N-is-0 ) |
| imm13 | ( n -- n ) |
| imm13-range | ( value -- * ) |
| imm13>parts-64 | ( imm13 -- imms immr N ) |
| imm14 | ( n -- n ) |
| imm14-range | ( value -- * ) |
| imm16 | ( n -- n ) |
| imm16-range | ( value -- * ) |
| imm19 | ( n -- n ) |
| imm19-range | ( value -- * ) |
| imm26 | ( n -- n ) |
| imm26-range | ( value -- * ) |
| imm3 | ( n -- n ) |
| imm3-range | ( value -- * ) |
| imm4 | ( n -- n ) |
| imm4-range | ( value -- * ) |
| imm5 | ( n -- n ) |
| imm5-range | ( value -- * ) |
| imm6 | ( n -- n ) |
| imm6-range | ( value -- * ) |
| imm7 | ( n -- n ) |
| imm7-range | ( value -- * ) |
| imm9 | ( n -- n ) |
| imm9-range | ( value -- * ) |
| immhi19 | ( n -- n ) |
| immhi19-range | ( value -- * ) |
| immlo2 | ( n -- n ) |
| immlo2-range | ( value -- * ) |
| immr | ( n -- n ) |
| immr-range | ( value -- * ) |
| immrimms | ( n -- n ) |
| immrimms-range | ( value -- * ) |
| imms | ( n -- n ) |
| imms-range | ( value -- * ) |
| make-checker-word | ( word n -- ) |
| make-integer-literal | ( string -- integer-literal ) |
| make-register-checker-word | ( word n -- ) |
| mask4 | ( n -- n ) |
| mask4-range | ( value -- * ) |
| no-field-word | ( vocab name -- * ) |
| nzcv | ( n -- n ) |
| nzcv-range | ( value -- * ) |
| nzcv4 | ( n -- n ) |
| nzcv4-range | ( value -- * ) |
| o0 | ( n -- n ) |
| o0-range | ( value -- * ) |
| op1 | ( n -- n ) |
| op1-range | ( value -- * ) |
| op10 | ( n -- n ) |
| op10-range | ( value -- * ) |
| op2 | ( n -- n ) |
| op2-range | ( value -- * ) |
| op3 | ( n -- n ) |
| op3-range | ( value -- * ) |
| op4 | ( n -- n ) |
| op4-range | ( value -- * ) |
| op5 | ( n -- n ) |
| op5-range | ( value -- * ) |
| op6 | ( n -- n ) |
| op6-range | ( value -- * ) |
| op7 | ( n -- n ) |
| op7-range | ( value -- * ) |
| op8 | ( n -- n ) |
| op8-range | ( value -- * ) |
| op9 | ( n -- n ) |
| op9-range | ( value -- * ) |
| opc1 | ( n -- n ) |
| opc1-range | ( value -- * ) |
| opc2 | ( n -- n ) |
| opc2-range | ( value -- * ) |
| opc3 | ( n -- n ) |
| opc3-range | ( value -- * ) |
| opc4 | ( n -- n ) |
| opc4-range | ( value -- * ) |
| option1 | ( n -- n ) |
| option1-range | ( value -- * ) |
| option2 | ( n -- n ) |
| option2-range | ( value -- * ) |
| option3 | ( n -- n ) |
| option3-range | ( value -- * ) |
| option4 | ( n -- n ) |
| option4-range | ( value -- * ) |
| option5 | ( n -- n ) |
| option5-range | ( value -- * ) |
| sf | ( n -- n ) |
| sf-range | ( value -- * ) |
| shift2 | ( n -- n ) |
| shift2-range | ( value -- * ) |
| simm7 | ( n -- n ) |
| simm7-range | ( value -- * ) |
| size1 | ( n -- n ) |
| size1-range | ( value -- * ) |
| size2 | ( n -- n ) |
| size2-range | ( value -- * ) |
| uimm4 | ( n -- n ) |
| uimm4-range | ( value -- * ) |
| uimm6 | ( n -- n ) |
| uimm6-range | ( value -- * ) |
Class predicate words
| Word | Stack effect |
| A-range? | ( object -- ? ) |
| CRm-range? | ( object -- ? ) |
| CRm4-range? | ( object -- ? ) |
| CRn-range? | ( object -- ? ) |
| CRn4-range? | ( object -- ? ) |
| D-range? | ( object -- ? ) |
| ELR_EL1? | ( object -- ? ) |
| ELR_EL2? | ( object -- ? ) |
| ELR_EL3? | ( object -- ? ) |
| L-range? | ( object -- ? ) |
| M-range? | ( object -- ? ) |
| N-range? | ( object -- ? ) |
| Nimmrimms-range? | ( object -- ? ) |
| Q-range? | ( object -- ? ) |
| Ra-range? | ( object -- ? ) |
| Rd-range? | ( object -- ? ) |
| Rm-range? | ( object -- ? ) |
| Rn-range? | ( object -- ? ) |
| Rs-range? | ( object -- ? ) |
| Rt-range? | ( object -- ? ) |
| Rt2-range? | ( object -- ? ) |
| S-range? | ( object -- ? ) |
| SPSR_EL1? | ( object -- ? ) |
| SPSR_EL2? | ( object -- ? ) |
| SPSR_EL3? | ( object -- ? ) |
| SP_EL0? | ( object -- ? ) |
| SP_EL1? | ( object -- ? ) |
| SP_EL2? | ( object -- ? ) |
| SP_EL3? | ( object -- ? ) |
| U-range? | ( object -- ? ) |
| Xd-range? | ( object -- ? ) |
| Xm-range? | ( object -- ? ) |
| Xn-range? | ( object -- ? ) |
| Xt-range? | ( object -- ? ) |
| Xt2-range? | ( object -- ? ) |
| Z-range? | ( object -- ? ) |
| a1-range? | ( object -- ? ) |
| b1-range? | ( object -- ? ) |
| b40-range? | ( object -- ? ) |
| bad-instruction? | ( object -- ? ) |
| c1-range? | ( object -- ? ) |
| cmode4-range? | ( object -- ? ) |
| cond4-range? | ( object -- ? ) |
| d1-range? | ( object -- ? ) |
| e1-range? | ( object -- ? ) |
| f1-range? | ( object -- ? ) |
| g1-range? | ( object -- ? ) |
| h1-range? | ( object -- ? ) |
| hw2-range? | ( object -- ? ) |
| imm12-range? | ( object -- ? ) |
| imm13-range? | ( object -- ? ) |
| imm14-range? | ( object -- ? ) |
| imm16-range? | ( object -- ? ) |
| imm19-range? | ( object -- ? ) |
| imm26-range? | ( object -- ? ) |
| imm3-range? | ( object -- ? ) |
| imm4-range? | ( object -- ? ) |
| imm5-range? | ( object -- ? ) |
| imm6-range? | ( object -- ? ) |
| imm7-range? | ( object -- ? ) |
| imm9-range? | ( object -- ? ) |
| immhi19-range? | ( object -- ? ) |
| immlo2-range? | ( object -- ? ) |
| immr-range? | ( object -- ? ) |
| immrimms-range? | ( object -- ? ) |
| imms-range? | ( object -- ? ) |
| integer-literal? | ( object -- ? ) |
| mask4-range? | ( object -- ? ) |
| no-field-word? | ( object -- ? ) |
| nzcv-range? | ( object -- ? ) |
| nzcv4-range? | ( object -- ? ) |
| o0-range? | ( object -- ? ) |
| op1-range? | ( object -- ? ) |
| op10-range? | ( object -- ? ) |
| op2-range? | ( object -- ? ) |
| op3-range? | ( object -- ? ) |
| op4-range? | ( object -- ? ) |
| op5-range? | ( object -- ? ) |
| op6-range? | ( object -- ? ) |
| op7-range? | ( object -- ? ) |
| op8-range? | ( object -- ? ) |
| op9-range? | ( object -- ? ) |
| opc1-range? | ( object -- ? ) |
| opc2-range? | ( object -- ? ) |
| opc3-range? | ( object -- ? ) |
| opc4-range? | ( object -- ? ) |
| option1-range? | ( object -- ? ) |
| option2-range? | ( object -- ? ) |
| option3-range? | ( object -- ? ) |
| option4-range? | ( object -- ? ) |
| option5-range? | ( object -- ? ) |
| sf-range? | ( object -- ? ) |
| shift2-range? | ( object -- ? ) |
| simm7-range? | ( object -- ? ) |
| size1-range? | ( object -- ? ) |
| size2-range? | ( object -- ? ) |
| uimm4-range? | ( object -- ? ) |
| uimm6-range? | ( object -- ? ) |
Files